1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * Configuation settings for the AT91SAM9261EK board.
13 /* ARM asynchronous clock */
14 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
15 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
17 #include <asm/hardware.h>
24 #define LCD_BPP LCD_COLOR8
27 #define CONFIG_SYS_SDRAM_BASE 0x20000000
28 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
29 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
30 #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
33 #ifdef CONFIG_CMD_NAND
34 #define CONFIG_SYS_MAX_NAND_DEVICE 1
35 #define CONFIG_SYS_NAND_BASE 0x40000000
36 #define CONFIG_SYS_NAND_DBW_8
38 #define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
40 #define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
41 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
42 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
47 #define CONFIG_DM9000_BASE 0x30000000
48 #define DM9000_IO CONFIG_DM9000_BASE
49 #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
50 #define CONFIG_DM9000_USE_16BIT
51 #define CONFIG_DM9000_NO_SROM
54 #define CONFIG_USB_ATMEL
55 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
56 #define CONFIG_USB_OHCI_NEW
57 #define CONFIG_SYS_USB_OHCI_CPU_INIT
58 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
59 #ifdef CONFIG_AT91SAM9G10EK
60 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10"
62 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
64 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2