1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards.
14 * SoC must be defined first, before hardware.h is included.
15 * In this case SoC is defined in boards.cfg.
17 #include <asm/hardware.h>
20 * Warning: changing CONFIG_SYS_TEXT_BASE requires
21 * adapting the initial boot program.
22 * Since the linker has to swallow that define, we must use a pure
26 /* ARM asynchronous clock */
27 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
28 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
31 * SDRAM: 1 bank, min 32, max 128 MB
32 * Initialized before u-boot gets started.
34 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
35 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
38 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
39 * leaving the correct space for initial global data structure above
40 * that address while providing maximum stack area below.
42 #ifdef CONFIG_AT91SAM9XE
43 # define CONFIG_SYS_INIT_SP_ADDR \
44 (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
46 # define CONFIG_SYS_INIT_SP_ADDR \
47 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
51 #ifdef CONFIG_CMD_NAND
52 #define CONFIG_SYS_MAX_NAND_DEVICE 1
53 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
54 #define CONFIG_SYS_NAND_DBW_8
55 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
56 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
57 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
58 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
62 #define CONFIG_USB_ATMEL
63 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
64 #define CONFIG_USB_OHCI_NEW 1
65 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
66 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
67 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
68 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2