2 * Rick Bronson <rick@efn.org>
4 * Configuation settings for the AT91RM9200DK board.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * If we are developing, we might want to start armboot from ram
30 * so we MUST NOT initialize critical regs like mem-timing ...
32 #define CONFIG_INIT_CRITICAL /* undef for developing */
34 /* ARM asynchronous clock */
35 #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
36 #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
37 /* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
39 #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
40 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42 #define CONFIG_SETUP_MEMORY_TAGS 1
43 #define CONFIG_INITRD_TAG 1
46 * Size of malloc() pool
48 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
49 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
51 #define CONFIG_BAUDRATE 115200
57 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
59 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
61 #define CONFIG_BOOTDELAY 3
62 /* #define CONFIG_ENV_OVERWRITE 1 */
64 #define CONFIG_COMMANDS \
69 CFG_CMD_AUTOSCRIPT | \
74 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
75 #include <cmd_confdefs.h>
77 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
78 #define SECTORSIZE 512
82 #define ADDR_COLUMN_PAGE 3
84 #define NAND_ChipID_UNKNOWN 0x00
85 #define NAND_MAX_FLOORS 1
86 #define NAND_MAX_CHIPS 1
88 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
89 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
91 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
92 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
94 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
96 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
97 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
98 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
99 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
100 /* the following are NOP's in our implementation */
101 #define NAND_CTL_CLRALE(nandptr)
102 #define NAND_CTL_SETALE(nandptr)
103 #define NAND_CTL_CLRCLE(nandptr)
104 #define NAND_CTL_SETCLE(nandptr)
106 #define CONFIG_NR_DRAM_BANKS 1
107 #define PHYS_SDRAM 0x20000000
108 #define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
110 #define CFG_MEMTEST_START PHYS_SDRAM
111 #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
113 #define CONFIG_DRIVER_ETHER
114 #define CONFIG_NET_RETRY_COUNT 20
115 #define CONFIG_AT91C_USE_RMII
117 #define CONFIG_HAS_DATAFLASH 1
118 #define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
119 #define CFG_MAX_DATAFLASH_BANKS 2
120 #define CFG_MAX_DATAFLASH_PAGES 16384
121 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
122 #define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
124 #define PHYS_FLASH_1 0x10000000
125 #define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
126 #define CFG_FLASH_BASE PHYS_FLASH_1
127 #define CFG_MAX_FLASH_BANKS 1
128 #define CFG_MAX_FLASH_SECT 40
129 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
130 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
132 #undef CFG_ENV_IS_IN_DATAFLASH
134 #ifdef CFG_ENV_IS_IN_DATAFLASH
135 #define CFG_ENV_OFFSET 0x20000
136 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
137 #define CFG_ENV_SIZE 0x2000 /* 0x8000 */
139 #define CFG_ENV_IS_IN_FLASH 1
140 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* 0x10000 */
141 #define CFG_ENV_SIZE 0x2000 /* 0x8000 */
145 #define CFG_LOAD_ADDR 0x21000000 /* default load address */
147 #define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
148 #define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
149 #define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
151 #define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
153 #define CFG_PROMPT "Uboot> " /* Monitor Command Prompt */
154 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
155 #define CFG_MAXARGS 16 /* max number of command args */
156 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
159 /*-----------------------------------------------------------------------
160 * Board specific extension for bd_info
162 * This structure is embedded in the global bd_info (bd_t) structure
163 * and can be used by the board specific code (eg board/...)
168 /* helper variable for board environment handling
170 * env_crc_valid == 0 => uninitialised
171 * env_crc_valid > 0 => environment crc in flash is valid
172 * env_crc_valid < 0 => environment crc in flash is invalid
178 #define CFG_HZ AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to
179 AT91C_TC_TIMER_DIV1_CLOCK */
181 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
183 #ifdef CONFIG_USE_IRQ
184 #error CONFIG_USE_IRQ not supported