3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
6 * 2004 (c) MontaVista Software, Inc.
8 * Configuation settings for the Intel Assabet board.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * High Level Configuration Options
36 #define CONFIG_SA1110 1 /* This is an SA1100 CPU */
37 #define CONFIG_ASSABET 1 /* on an Intel Assabet Board */
40 /* we will never enable dcache, because we have to setup MMU first */
41 #define CONFIG_SYS_NO_DCACHE
43 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
44 #define CONFIG_SETUP_MEMORY_TAGS 1
45 #define CONFIG_INITRD_TAG 1
48 * Size of malloc() pool
50 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
51 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size rsrvd for initial data */
56 #define CONFIG_NET_MULTI
57 #define CONFIG_LAN91C96 /* we have an SMC9194 on-board */
58 #define CONFIG_LAN91C96_BASE 0x18000000
61 * select serial console configuration
63 #define CONFIG_SA1100_SERIAL
64 #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */
66 /* allow to overwrite serial and ethaddr */
67 #define CONFIG_ENV_OVERWRITE
69 #define CONFIG_BAUDRATE 115200
73 * Command line configuration.
75 #include <config_cmd_default.h>
77 #define CONFIG_CMD_DHCP
83 #define CONFIG_BOOTP_SUBNETMASK
84 #define CONFIG_BOOTP_GATEWAY
85 #define CONFIG_BOOTP_HOSTNAME
86 #define CONFIG_BOOTP_BOOTPATH
89 #define CONFIG_BOOTDELAY 3
90 #define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp"
91 #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
92 #define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
94 #if defined(CONFIG_CMD_KGDB)
95 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
96 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
100 * Miscellaneous configurable options
102 #define CONFIG_SYS_LONGHELP /* undef to save memory */
103 #define CONFIG_SYS_PROMPT "Intel Assabet # " /* Monitor Command Prompt */
104 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
105 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
106 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
107 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
109 #define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */
110 #define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
112 #define CONFIG_SYS_LOAD_ADDR 0xc0000000 /* default load address */
114 #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
115 #define CONFIG_SYS_CPUSPEED 0x0a /* set core clock to 206MHz */
117 /* valid baudrates */
118 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
120 /*-----------------------------------------------------------------------
123 * The stack sizes are set up in start.S using the settings below
125 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
126 #ifdef CONFIG_USE_IRQ
127 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
128 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
131 /*-----------------------------------------------------------------------
132 * Physical Memory Map
134 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
135 #define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
136 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
138 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
139 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
140 #define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
141 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
143 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
144 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
146 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
147 #define CONFIG_SYS_RAMSTART
150 /*-----------------------------------------------------------------------
151 * FLASH and environment organization
154 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
155 #define CONFIG_SYS_FLASH_SIZE PHYS_FLASH_SIZE
156 #define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
157 #define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
158 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
159 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
160 #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
161 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
162 #undef CONFIG_SYS_FLASH_PROTECTION
163 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
165 #define CONFIG_ENV_IS_IN_FLASH 1
167 #if defined(CONFIG_ENV_IS_IN_FLASH)
168 #define CONFIG_ENV_IN_OWN_SECTOR 1
169 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
170 #define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE
171 #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
174 #endif /* __CONFIG_H */