board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks
[platform/kernel/u-boot.git] / include / configs / aspeed-common.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2012-2020  ASPEED Technology Inc.
4  * Ryan Chen <ryan_chen@aspeedtech.com>
5  *
6  * Copyright 2016 IBM Corporation
7  * (C) Copyright 2016 Google, Inc
8  */
9
10 #ifndef _ASPEED_COMMON_CONFIG_H
11 #define _ASPEED_COMMON_CONFIG_H
12
13 #include <asm/arch/platform.h>
14
15 /* Misc CPU related */
16
17 #define CONFIG_SYS_SDRAM_BASE           ASPEED_DRAM_BASE
18
19 #ifdef CONFIG_PRE_CON_BUF_SZ
20 #define CONFIG_SYS_INIT_RAM_ADDR        (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
21 #define CONFIG_SYS_INIT_RAM_SIZE        (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
22 #else
23 #define CONFIG_SYS_INIT_RAM_ADDR        (ASPEED_SRAM_BASE)
24 #define CONFIG_SYS_INIT_RAM_SIZE        (ASPEED_SRAM_SIZE)
25 #endif
26
27 #define SYS_INIT_RAM_END                (CONFIG_SYS_INIT_RAM_ADDR \
28                                          + CONFIG_SYS_INIT_RAM_SIZE)
29 #define CONFIG_SYS_INIT_SP_ADDR         (SYS_INIT_RAM_END \
30                                          - GENERATED_GBL_DATA_SIZE)
31
32 /*
33  * NS16550 Configuration
34  */
35
36 #endif  /* __AST_COMMON_CONFIG_H */