1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 * Configuration settings for the Freescale i.MX6DL aristainetos2 board.
11 #ifndef __ARISTAINETOS2_CONFIG_H
12 #define __ARISTAINETOS2_CONFIG_H
14 #define CONFIG_HOSTNAME "aristainetos2"
16 #define CONFIG_MXC_UART_BASE UART2_BASE
17 #define CONSOLE_DEV "ttymxc1"
19 #define CONFIG_FEC_XCV_TYPE RGMII
21 #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
22 "board_type=aristainetos2_7@1\0" \
23 "nor_bootdelay=-2\0" \
24 "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \
25 "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \
26 "-(rescue-system);gpmi-nand:-(ubi)\0" \
27 "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \
28 "ubiargs=setenv bootargs console=${console},${baudrate} " \
29 "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \
30 "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \
31 "ubifsload ${fit_addr_r} /boot/system.itb; " \
32 "imi ${fit_addr_r}\0 "
34 #define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15)
37 #define CONFIG_SYS_LDB_CLOCK 33246000
40 #include "mx6_common.h"
42 #define CONFIG_MACH_TYPE 4501
43 #define CONFIG_MMCROOT "/dev/mmcblk0p1"
46 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
48 #define IMX_FEC_BASE ENET_BASE_ADDR
49 #define CONFIG_ETHPRIME "FEC"
50 #define CONFIG_FEC_MXC_PHYADDR 0
52 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
54 #define CONFIG_EXTRA_ENV_SETTINGS \
55 "disable_giga=yes\0" \
56 "script=u-boot.scr\0" \
57 "fit_file=/boot/system.itb\0" \
58 "loadaddr=0x12000000\0" \
59 "fit_addr_r=0x14000000\0" \
60 "uboot=/boot/u-boot.imx\0" \
62 "rescue_sys_addr=f0000\0" \
63 "rescue_sys_length=f10000\0" \
66 "console=" CONSOLE_DEV "\0" \
67 "fdt_high=0xffffffff\0" \
68 "initrd_high=0xffffffff\0" \
69 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
70 "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \
71 "default ${board_type}\0" \
72 "get_env=mw ${loadaddr} 0 0x20000;" \
74 "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \
75 "env import -t ${loadaddr}\0" \
76 "default_env=mw ${loadaddr} 0 0x20000;" \
77 "env export -t ${loadaddr} serial# ethaddr eth1addr " \
80 "env import -t ${loadaddr}\0" \
82 "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
83 "bootscript=echo Running bootscript from mmc ...; " \
87 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
88 "mmcargs=setenv bootargs console=${console},${baudrate} " \
90 "mmcboot=echo Booting from mmc ...; " \
91 "run mmcargs addmtd addmisc set_fit_default;" \
92 "bootm ${fit_addr_r}\0" \
93 "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
95 "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
97 "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
98 "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \
99 "setexpr uboot_maxsize ${uboot_sz} - 400;" \
100 "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \
101 "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
102 "sf write ${loadaddr} 400 ${filesize};" \
103 "sf read ${cmp_buf} 400 ${uboot_sz};" \
104 "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \
105 "ubiboot=echo Booting from ubi ...; " \
106 "run ubiargs addmtd addmisc set_fit_default;" \
107 "bootm ${fit_addr_r}\0" \
108 "rescueargs=setenv bootargs console=${console},${baudrate} " \
109 "root=/dev/ram rw\0 " \
110 "rescueboot=echo Booting rescue system from NOR ...; " \
111 "run rescueargs addmtd addmisc set_fit_default;" \
112 "bootm ${fit_addr_r}\0" \
113 "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \
114 "${rescue_sys_length}; imi ${fit_addr_r}\0" \
115 CONFIG_EXTRA_ENV_BOARD_SETTINGS
117 #define CONFIG_BOOTCOMMAND \
118 "mmc dev ${mmcdev};" \
119 "if mmc rescan; then " \
120 "if run loadbootscript; then " \
123 "if run mmc_load_fit; then " \
126 "if run ubifs_load_fit; then " \
129 "if run rescue_load_fit; then " \
132 "echo RESCUE SYSTEM BOOT " \
139 "if run ubifs_load_fit; then " \
142 "if run rescue_load_fit; then " \
145 "echo RESCUE SYSTEM BOOT FAILURE;" \
150 #define CONFIG_ARP_TIMEOUT 200UL
152 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
153 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
154 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
156 /* Physical Memory Map */
157 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
159 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
160 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
161 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
163 #define CONFIG_SYS_INIT_SP_OFFSET \
164 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
165 #define CONFIG_SYS_INIT_SP_ADDR \
166 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
168 #define CONFIG_SYS_FSL_USDHC_NUM 2
171 #define CONFIG_SYS_I2C
172 #define CONFIG_SYS_I2C_SPEED 100000
173 #define CONFIG_SYS_I2C_SLAVE 0x7f
174 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} }
177 #define CONFIG_SYS_MAX_NAND_DEVICE 1
178 #define CONFIG_SYS_NAND_BASE 0x40000000
179 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
180 #define CONFIG_SYS_NAND_ONFI_DETECTION
182 /* DMA stuff, needed for GPMI/MXS NAND support */
185 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
186 #define CONFIG_SYS_RTC_BUS_NUM 2
187 #define CONFIG_RTC_M41T11
190 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
191 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
192 #define CONFIG_MXC_USB_FLAGS 0
197 /* check this console not needed, after test remove it */
198 #define CONFIG_VIDEO_BMP_RLE8
199 #define CONFIG_SPLASH_SCREEN
200 #define CONFIG_SPLASH_SCREEN_ALIGN
201 #define CONFIG_BMP_16BPP
202 #define CONFIG_VIDEO_LOGO
203 #define CONFIG_VIDEO_BMP_LOGO
204 #define CONFIG_IMX_VIDEO_SKIP
206 #define CONFIG_IMX6_PWM_PER_CLK 66000000
209 #endif /* __ARISTAINETOS2_CONFIG_H */