4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 * Configuration settings for the Freescale i.MX6Q SabreSD board.
11 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __ARISTAINETOS_COMMON_CONFIG_H
14 #define __ARISTAINETOS_COMMON_CONFIG_H
16 #include "mx6_common.h"
18 #define CONFIG_MACH_TYPE 4501
19 #define CONFIG_MMCROOT "/dev/mmcblk0p1"
20 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
22 /* Size of malloc() pool */
23 #define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M)
25 #define CONFIG_BOARD_EARLY_INIT_F
27 #define CONFIG_MXC_UART
29 #define CONFIG_CMD_FUSE
30 #define CONFIG_MXC_OCOTP
33 #define CONFIG_FSL_ESDHC
34 #define CONFIG_FSL_USDHC
35 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
38 #define CONFIG_CMD_MMC
39 #define CONFIG_GENERIC_MMC
40 #define CONFIG_BOUNCE_BUFFER
41 #define CONFIG_CMD_EXT2
42 #define CONFIG_CMD_FAT
43 #define CONFIG_DOS_PARTITION
45 #define CONFIG_CMD_PING
46 #define CONFIG_CMD_DHCP
47 #define CONFIG_CMD_MII
48 #define CONFIG_CMD_NET
49 #define CONFIG_FEC_MXC
51 #define IMX_FEC_BASE ENET_BASE_ADDR
52 #define CONFIG_ETHPRIME "FEC"
53 #define CONFIG_FEC_MXC_PHYADDR 0
56 #define CONFIG_PHY_MICREL
59 #define CONFIG_SPI_FLASH
60 #define CONFIG_SPI_FLASH_MTD
61 #define CONFIG_SPI_FLASH_STMICRO
62 #define CONFIG_MXC_SPI
63 #define CONFIG_SF_DEFAULT_BUS 3
64 #define CONFIG_SF_DEFAULT_SPEED 20000000
65 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
66 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
68 /* allow to overwrite serial and ethaddr */
69 #define CONFIG_ENV_OVERWRITE
70 #define CONFIG_CONS_INDEX 1
71 #define CONFIG_BAUDRATE 115200
73 /* Command definition */
74 #define CONFIG_CMD_BMODE
75 #define CONFIG_CMD_BOOTZ
76 #define CONFIG_CMD_SETEXPR
78 #define CONFIG_BOOTDELAY 3
80 #define CONFIG_LOADADDR 0x12000000
81 #define CONFIG_SYS_TEXT_BASE 0x17800000
83 #define CONFIG_EXTRA_ENV_SETTINGS \
84 "script=u-boot.scr\0" \
85 "fit_file=/boot/system.itb\0" \
86 "loadaddr=0x12000000\0" \
87 "fit_addr_r=0x14000000\0" \
88 "uboot=/boot/u-boot.imx\0" \
90 "rescue_sys_addr=f0000\0" \
91 "rescue_sys_length=f10000\0" \
94 "console=" CONFIG_CONSOLE_DEV "\0" \
95 "fdt_high=0xffffffff\0" \
96 "initrd_high=0xffffffff\0" \
97 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
98 "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \
99 "default ${board_type}\0" \
100 "get_env=mw ${loadaddr} 0 0x20000;" \
102 "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \
103 "env import -t ${loadaddr}\0" \
104 "default_env=mw ${loadaddr} 0 0x20000;" \
105 "env export -t ${loadaddr} serial# ethaddr eth1addr " \
106 "board_type panel;" \
108 "env import -t ${loadaddr}\0" \
110 "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
111 "bootscript=echo Running bootscript from mmc ...; " \
115 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
116 "mmcargs=setenv bootargs console=${console},${baudrate} " \
117 "root=${mmcroot}\0" \
118 "mmcboot=echo Booting from mmc ...; " \
119 "run mmcargs addmtd addmisc set_fit_default;" \
120 "bootm ${fit_addr_r}\0" \
121 "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
123 "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
125 "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
126 "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \
127 "setexpr uboot_maxsize ${uboot_sz} - 400;" \
128 "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \
129 "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
130 "sf write ${loadaddr} 400 ${filesize};" \
131 "sf read ${cmp_buf} 400 ${uboot_sz};" \
132 "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \
133 "ubiboot=echo Booting from ubi ...; " \
134 "run ubiargs addmtd addmisc set_fit_default;" \
135 "bootm ${fit_addr_r}\0" \
136 "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \
137 "ubifsload ${fit_addr_r} /boot/system.itb; " \
138 "imi ${fit_addr_r}\0 " \
139 "rescueargs=setenv bootargs console=${console},${baudrate} " \
140 "root=/dev/ram rw\0 " \
141 "rescueboot=echo Booting rescue system from NOR ...; " \
142 "run rescueargs addmtd addmisc set_fit_default;" \
143 "bootm ${fit_addr_r}\0" \
144 "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \
145 "${rescue_sys_length}; imi ${fit_addr_r}\0" \
146 CONFIG_EXTRA_ENV_BOARD_SETTINGS
148 #define CONFIG_BOOTCOMMAND \
149 "mmc dev ${mmcdev};" \
150 "if mmc rescan; then " \
151 "if run loadbootscript; then " \
154 "if run mmc_load_fit; then " \
157 "if run ubifs_load_fit; then " \
160 "if run rescue_load_fit; then " \
163 "echo RESCUE SYSTEM BOOT " \
170 "if run ubifs_load_fit; then " \
173 "if run rescue_load_fit; then " \
176 "echo RESCUE SYSTEM BOOT FAILURE;" \
181 #define CONFIG_ARP_TIMEOUT 200UL
183 /* Miscellaneous configurable options */
184 #define CONFIG_SYS_LONGHELP
185 #define CONFIG_SYS_HUSH_PARSER
186 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
187 #define CONFIG_AUTO_COMPLETE
188 #define CONFIG_SYS_CBSIZE 256
190 /* Print Buffer Size */
191 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
192 #define CONFIG_SYS_MAXARGS 16
193 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
195 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
196 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
197 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
199 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
201 #define CONFIG_CMDLINE_EDITING
202 #define CONFIG_STACKSIZE (128 * 1024)
204 /* Physical Memory Map */
205 #define CONFIG_NR_DRAM_BANKS 1
206 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
208 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
209 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
210 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
212 #define CONFIG_SYS_INIT_SP_OFFSET \
213 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
214 #define CONFIG_SYS_INIT_SP_ADDR \
215 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
217 /* Environment organization */
218 #define CONFIG_ENV_SIZE (12 * 1024)
219 #define CONFIG_ENV_IS_IN_SPI_FLASH
220 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
221 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
222 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
223 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
224 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
225 #define CONFIG_ENV_SECT_SIZE (0x010000)
226 #define CONFIG_ENV_OFFSET (0x0d0000)
227 #define CONFIG_ENV_OFFSET_REDUND (0x0e0000)
229 #define CONFIG_OF_LIBFDT
231 #define CONFIG_CMD_CACHE
233 #define CONFIG_SYS_FSL_USDHC_NUM 2
236 #define CONFIG_CMD_I2C
237 #define CONFIG_SYS_I2C
238 #define CONFIG_SYS_I2C_MXC
239 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
240 #define CONFIG_SYS_I2C_SPEED 100000
241 #define CONFIG_SYS_I2C_SLAVE 0x7f
242 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} }
245 #define CONFIG_CMD_NAND
246 #define CONFIG_CMD_NAND_TRIMFFS
247 #define CONFIG_NAND_MXS
248 #define CONFIG_SYS_MAX_NAND_DEVICE 1
249 #define CONFIG_SYS_NAND_BASE 0x40000000
250 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
251 #define CONFIG_SYS_NAND_ONFI_DETECTION
253 /* DMA stuff, needed for GPMI/MXS NAND support */
254 #define CONFIG_APBH_DMA
255 #define CONFIG_APBH_DMA_BURST
256 #define CONFIG_APBH_DMA_BURST8
259 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
260 #define CONFIG_SYS_RTC_BUS_NUM 2
261 #define CONFIG_RTC_M41T11
262 #define CONFIG_CMD_DATE
265 #define CONFIG_CMD_USB
266 #define CONFIG_CMD_FAT
267 #define CONFIG_USB_EHCI
268 #define CONFIG_USB_EHCI_MX6
269 #define CONFIG_USB_STORAGE
270 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
271 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
272 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
273 #define CONFIG_MXC_USB_FLAGS 0
276 #define CONFIG_CMD_MTDPARTS
277 #define CONFIG_MTD_PARTITIONS
278 #define CONFIG_MTD_DEVICE
279 #define CONFIG_RBTREE
281 #define CONFIG_CMD_UBI
282 #define CONFIG_CMD_UBIFS
284 #define CONFIG_MTD_UBI_FASTMAP
285 #define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1
287 #define CONFIG_HW_WATCHDOG
288 #define CONFIG_IMX_WATCHDOG
294 #define CONFIG_VIDEO_IPUV3
295 /* check this console not needed, after test remove it */
296 #define CONFIG_CFB_CONSOLE
297 #define CONFIG_VGA_AS_SINGLE_DEVICE
298 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
299 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
300 #define CONFIG_VIDEO_BMP_RLE8
301 #define CONFIG_SPLASH_SCREEN
302 #define CONFIG_SPLASH_SCREEN_ALIGN
303 #define CONFIG_BMP_16BPP
304 #define CONFIG_VIDEO_LOGO
305 #define CONFIG_VIDEO_BMP_LOGO
306 #define CONFIG_IPUV3_CLK 198000000
307 #define CONFIG_IMX_VIDEO_SKIP
309 #define CONFIG_CMD_BMP
311 #define CONFIG_PWM_IMX
312 #define CONFIG_IMX6_PWM_PER_CLK 66000000
314 #endif /* __ARISTAINETOS_COMMON_CONFIG_H */