Merge branch 'master' of git://git.denx.de/u-boot-i2c
[platform/kernel/u-boot.git] / include / configs / aria.h
1 /*
2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3  * (C) Copyright 2009, DAVE Srl <www.dave.eu>
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 /*
25  * Aria board configuration file
26  */
27
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30
31 #define CONFIG_ARIA 1
32 /*
33  * Memory map for the ARIA board:
34  *
35  * 0x0000_0000-0x0FFF_FFFF      DDR RAM (256 MB)
36  * 0x3000_0000-0x3001_FFFF      On Chip SRAM (128 KB)
37  * 0x3010_0000-0x3011_FFFF      On Board SRAM (128 KB) - CS6
38  * 0x3020_0000-0x3021_FFFF      FPGA (128 KB) - CS2
39  * 0x8000_0000-0x803F_FFFF      IMMR (4 MB)
40  * 0x8400_0000-0x82FF_FFFF      PCI I/O space (16 MB)
41  * 0xA000_0000-0xAFFF_FFFF      PCI memory space (256 MB)
42  * 0xB000_0000-0xBFFF_FFFF      PCI memory mapped I/O space (256 MB)
43  * 0xFC00_0000-0xFFFF_FFFF      NOR Boot FLASH (64 MB)
44  */
45
46 /*
47  * High Level Configuration Options
48  */
49 #define CONFIG_E300             1       /* E300 Family */
50 #define CONFIG_MPC512X          1       /* MPC512X family */
51 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
52 #define CONFIG_FSL_DIU_LOGO_BMP 1       /* Don't include FSL DIU binary bmp */
53
54 /* video */
55 #undef CONFIG_VIDEO
56
57 #if defined(CONFIG_VIDEO)
58 #define CONFIG_CFB_CONSOLE
59 #define CONFIG_VGA_AS_SINGLE_DEVICE
60 #endif
61
62 /* CONFIG_PCI is defined at config time */
63
64 #define CONFIG_SYS_MPC512X_CLKIN        33000000        /* in Hz */
65
66 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
67 #define CONFIG_MISC_INIT_R
68
69 #define CONFIG_SYS_IMMR                 0x80000000
70 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR+0x2100)
71
72 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
73 #define CONFIG_SYS_MEMTEST_END          0x00400000
74
75 /*
76  * DDR Setup - manually set all parameters as there's no SPD etc.
77  */
78 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
79 #define CONFIG_SYS_DDR_BASE             0x00000000
80 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
81
82 /* DDR Controller Configuration
83  *
84  * SYS_CFG:
85  *      [31:31] MDDRC Soft Reset:       Diabled
86  *      [30:30] DRAM CKE pin:           Enabled
87  *      [29:29] DRAM CLK:               Enabled
88  *      [28:28] Command Mode:           Enabled (For initialization only)
89  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
90  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
91  *      [20:19] Read Test:              DON'T USE
92  *      [18:18] Self Refresh:           Enabled
93  *      [17:17] 16bit Mode:             Disabled
94  *      [16:13] Ready Delay:            2
95  *      [12:12] Half DQS Delay:         Disabled
96  *      [11:11] Quarter DQS Delay:      Disabled
97  *      [10:08] Write Delay:            2
98  *      [07:07] Early ODT:              Disabled
99  *      [06:06] On DIE Termination:     Disabled
100  *      [05:05] FIFO Overflow Clear:    DON'T USE here
101  *      [04:04] FIFO Underflow Clear:   DON'T USE here
102  *      [03:03] FIFO Overflow Pending:  DON'T USE here
103  *      [02:02] FIFO Underlfow Pending: DON'T USE here
104  *      [01:01] FIFO Overlfow Enabled:  Enabled
105  *      [00:00] FIFO Underflow Enabled: Enabled
106  * TIME_CFG0
107  *      [31:16] DRAM Refresh Time:      0 CSB clocks
108  *      [15:8]  DRAM Command Time:      0 CSB clocks
109  *      [07:00] DRAM Precharge Time:    0 CSB clocks
110  * TIME_CFG1
111  *      [31:26] DRAM tRFC:
112  *      [25:21] DRAM tWR1:
113  *      [20:17] DRAM tWRT1:
114  *      [16:11] DRAM tDRR:
115  *      [10:05] DRAM tRC:
116  *      [04:00] DRAM tRAS:
117  * TIME_CFG2
118  *      [31:28] DRAM tRCD:
119  *      [27:23] DRAM tFAW:
120  *      [22:19] DRAM tRTW1:
121  *      [18:15] DRAM tCCD:
122  *      [14:10] DRAM tRTP:
123  *      [09:05] DRAM tRP:
124  *      [04:00] DRAM tRPA
125  */
126 #define CONFIG_SYS_MDDRC_SYS_CFG     (  (1 << 31) |     /* RST_B */ \
127                                         (1 << 30) |     /* CKE */ \
128                                         (1 << 29) |     /* CLK_ON */ \
129                                         (1 << 28) |     /* CMD_MODE */ \
130                                         (4 << 25) |     /* DRAM_ROW_SELECT */ \
131                                         (3 << 21) |     /* DRAM_BANK_SELECT */ \
132                                         (0 << 18) |     /* SELF_REF_EN */ \
133                                         (0 << 17) |     /* 16BIT_MODE */ \
134                                         (2 << 13) |     /* RDLY */ \
135                                         (0 << 12) |     /* HALF_DQS_DLY */ \
136                                         (1 << 11) |     /* QUART_DQS_DLY */ \
137                                         (2 <<  8) |     /* WDLY */ \
138                                         (0 <<  7) |     /* EARLY_ODT */ \
139                                         (1 <<  6) |     /* ON_DIE_TERMINATE */ \
140                                         (0 <<  5) |     /* FIFO_OV_CLEAR */ \
141                                         (0 <<  4) |     /* FIFO_UV_CLEAR */ \
142                                         (0 <<  1) |     /* FIFO_OV_EN */ \
143                                         (0 <<  0)       /* FIFO_UV_EN */ \
144                                      )
145
146 #define CONFIG_SYS_MDDRC_SYS_CFG_RUN    (CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28))
147 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x55D81189
148 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34790863
149
150 #define CONFIG_SYS_MDDRC_SYS_CFG_EN     0xF0000000
151 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x00003D2E
152 #define CONFIG_SYS_MDDRC_TIME_CFG0_RUN  0x030C3D2E
153
154 #define CONFIG_SYS_MICRON_NOP           0x01380000
155 #define CONFIG_SYS_MICRON_PCHG_ALL      0x01100400
156 #define CONFIG_SYS_MICRON_EMR        (  (1 << 24) |     /* CMD_REQ */ \
157                                         (0 << 22) |     /* DRAM_CS */ \
158                                         (0 << 21) |     /* DRAM_RAS */ \
159                                         (0 << 20) |     /* DRAM_CAS */ \
160                                         (0 << 19) |     /* DRAM_WEB */ \
161                                         (1 << 16) |     /* DRAM_BS[2:0] */ \
162                                         (0 << 15) |     /* */ \
163                                         (0 << 12) |     /* A12->out */ \
164                                         (0 << 11) |     /* A11->RDQS */ \
165                                         (0 << 10) |     /* A10->DQS# */ \
166                                         (0 <<  7) |     /* OCD program */ \
167                                         (0 <<  6) |     /* Rtt1 */ \
168                                         (0 <<  3) |     /* posted CAS# */ \
169                                         (0 <<  2) |     /* Rtt0 */ \
170                                         (1 <<  1) |     /* ODS */ \
171                                         (0 <<  0)       /* DLL */ \
172                                      )
173 #define CONFIG_SYS_MICRON_EMR2          0x01020000
174 #define CONFIG_SYS_MICRON_EMR3          0x01030000
175 #define CONFIG_SYS_MICRON_RFSH          0x01080000
176 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
177 #define CONFIG_SYS_MICRON_EMR_OCD    (  (1 << 24) |     /* CMD_REQ */ \
178                                         (0 << 22) |     /* DRAM_CS */ \
179                                         (0 << 21) |     /* DRAM_RAS */ \
180                                         (0 << 20) |     /* DRAM_CAS */ \
181                                         (0 << 19) |     /* DRAM_WEB */ \
182                                         (1 << 16) |     /* DRAM_BS[2:0] */ \
183                                         (0 << 15) |     /* */ \
184                                         (0 << 12) |     /* A12->out */ \
185                                         (0 << 11) |     /* A11->RDQS */ \
186                                         (1 << 10) |     /* A10->DQS# */ \
187                                         (7 <<  7) |     /* OCD program */ \
188                                         (0 <<  6) |     /* Rtt1 */ \
189                                         (0 <<  3) |     /* posted CAS# */ \
190                                         (1 <<  2) |     /* Rtt0 */ \
191                                         (0 <<  1) |     /* ODS (Output Drive Strength) */ \
192                                         (0 <<  0)       /* DLL */ \
193                                      )
194
195 /*
196  * Backward compatible definitions,
197  * so we do not have to change cpu/mpc512x/fixed_sdram.c
198  */
199 #define CONFIG_SYS_MICRON_EM2           (CONFIG_SYS_MICRON_EMR2)
200 #define CONFIG_SYS_MICRON_EM3           (CONFIG_SYS_MICRON_EMR3)
201 #define CONFIG_SYS_MICRON_EN_DLL        (CONFIG_SYS_MICRON_EMR)
202 #define CONFIG_SYS_MICRON_OCD_DEFAULT   (CONFIG_SYS_MICRON_EMR_OCD)
203
204 /* DDR Priority Manager Configuration */
205 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
206 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
207 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
208 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
209 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
210 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
211 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
212 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
213 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
214 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
215 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
216 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
217 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
218 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
219 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
220 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
221 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
222 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
223 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
224 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
225 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
226 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
227 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
228
229 /*
230  * NOR FLASH on the Local Bus
231  */
232 #define CONFIG_SYS_FLASH_CFI                            /* use the CFI code */
233 #define CONFIG_FLASH_CFI_DRIVER                         /* use the CFI driver */
234 #define CONFIG_SYS_FLASH_BASE           0xF8000000      /* start of FLASH */
235 #define CONFIG_SYS_FLASH_SIZE           0x08000000      /* max flash size */
236
237 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
238 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
239 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
240 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* max sectors */
241
242 #undef CONFIG_SYS_FLASH_CHECKSUM
243
244 /*
245  * NAND FLASH support
246  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
247  */
248 #define CONFIG_CMD_NAND                                 /* enable NAND support */
249 #define CONFIG_JFFS2_NAND                               /* with JFFS2 on it */
250
251
252 #define CONFIG_NAND_MPC5121_NFC
253 #define CONFIG_SYS_NAND_BASE            0x40000000
254
255 #define CONFIG_SYS_MAX_NAND_DEVICE      1
256 #define NAND_MAX_CHIPS                  CONFIG_SYS_MAX_NAND_DEVICE
257
258 #define CONFIG_SYS_64BIT_VSPRINTF       /* needed for nand_util.c */
259
260 /*
261  * Configuration parameters for MPC5121 NAND driver
262  */
263 #define CONFIG_FSL_NFC_WIDTH            1
264 #define CONFIG_FSL_NFC_WRITE_SIZE       2048
265 #define CONFIG_FSL_NFC_SPARE_SIZE       64
266 #define CONFIG_FSL_NFC_CHIPS            CONFIG_SYS_MAX_NAND_DEVICE
267
268 #define CONFIG_SYS_SRAM_BASE            0x30000000
269 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
270
271 /* Make two SRAM regions contiguous */
272 #define CONFIG_SYS_ARIA_SRAM_BASE       (CONFIG_SYS_SRAM_BASE + \
273                                          CONFIG_SYS_SRAM_SIZE)
274 #define CONFIG_SYS_ARIA_SRAM_SIZE       0x00100000      /* reserve 1MB-window */
275
276 #define CONFIG_SYS_ARIA_FPGA_BASE       (CONFIG_SYS_ARIA_SRAM_BASE + \
277                                          CONFIG_SYS_ARIA_SRAM_SIZE)
278 #define CONFIG_SYS_ARIA_FPGA_SIZE       0x20000         /* 128 KB */
279
280 #define CONFIG_SYS_CS0_CFG              0x05059150
281 #define CONFIG_SYS_CS2_CFG              (       (5 << 24) | \
282                                                 (5 << 16) | \
283                                                 (1 << 15) | \
284                                                 (0 << 14) | \
285                                                 (0 << 13) | \
286                                                 (1 << 12) | \
287                                                 (0 << 10) | \
288                                                 (3 <<  8) | /* 32 bit */ \
289                                                 (0 <<  7) | \
290                                                 (1 <<  6) | \
291                                                 (1 <<  4) | \
292                                                 (0 <<  3) | \
293                                                 (0 <<  2) | \
294                                                 (0 <<  1) | \
295                                                 (0 <<  0)   \
296                                         )
297 #define CONFIG_SYS_CS6_CFG              0x05059150
298
299 /* Use alternative CS timing for CS0 and CS2 */
300 #define CONFIG_SYS_CS_ALETIMING 0x00000005
301
302 /* Use SRAM for initial stack */
303 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE
304 #define CONFIG_SYS_INIT_RAM_END         CONFIG_SYS_SRAM_SIZE
305
306 #define CONFIG_SYS_GBL_DATA_SIZE        0x100
307 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - \
308                                          CONFIG_SYS_GBL_DATA_SIZE)
309 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
310
311 #define CONFIG_SYS_MONITOR_BASE         TEXT_BASE
312 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
313
314 #ifdef  CONFIG_FSL_DIU_FB
315 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)
316 #else
317 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
318 #endif
319
320 /* FPGA */
321 #define CONFIG_ARIA_FPGA                1
322
323 /*
324  * Serial Port
325  */
326 #define CONFIG_CONS_INDEX               1
327 #undef CONFIG_SERIAL_SOFTWARE_FIFO
328
329 /*
330  * Serial console configuration
331  */
332 #define CONFIG_PSC_CONSOLE              3       /* console on PSC3 */
333 #if CONFIG_PSC_CONSOLE != 3
334 #error CONFIG_PSC_CONSOLE must be 3
335 #endif
336
337 #define CONFIG_BAUDRATE                 115200  /* ... at 115200 bps */
338 #define CONFIG_SYS_BAUDRATE_TABLE  \
339         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
340
341 #define CONSOLE_FIFO_TX_SIZE            FIFOC_PSC3_TX_SIZE
342 #define CONSOLE_FIFO_TX_ADDR            FIFOC_PSC3_TX_ADDR
343 #define CONSOLE_FIFO_RX_SIZE            FIFOC_PSC3_RX_SIZE
344 #define CONSOLE_FIFO_RX_ADDR            FIFOC_PSC3_RX_ADDR
345
346 #define CONFIG_CMDLINE_EDITING          1       /* command line history */
347 /* Use the HUSH parser */
348 #define CONFIG_SYS_HUSH_PARSER
349 #ifdef  CONFIG_SYS_HUSH_PARSER
350 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
351 #endif
352
353 /*
354  * PCI
355  */
356 #ifdef CONFIG_PCI
357
358 #define CONFIG_SYS_PCI_MEM_BASE         0xA0000000
359 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
360 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000      /* 256M */
361 #define CONFIG_SYS_PCI_MMIO_BASE        (CONFIG_SYS_PCI_MEM_BASE + \
362                                          CONFIG_SYS_PCI_MEM_SIZE)
363 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
364 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000      /* 256M */
365 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
366 #define CONFIG_SYS_PCI_IO_PHYS          0x84000000
367 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000      /* 16M */
368
369 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
370
371 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
372
373 #endif
374
375 /* I2C */
376 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
377 #undef CONFIG_SOFT_I2C                  /* so disable bit-banged I2C */
378 #define CONFIG_I2C_MULTI_BUS
379
380 /* I2C speed and slave address */
381 #define CONFIG_SYS_I2C_SPEED            100000
382 #define CONFIG_SYS_I2C_SLAVE            0x7F
383 #if 0
384 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
385 #endif
386
387 /*
388  * IIM - IC Identification Module
389  */
390 #undef CONFIG_IIM
391
392 /*
393  * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
394  * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
395  */
396 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
397 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
398 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
399 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
400
401 /*
402  * Ethernet configuration
403  */
404 #define CONFIG_MPC512x_FEC              1
405 #define CONFIG_NET_MULTI
406 #define CONFIG_PHY_ADDR                 0x17
407 #define CONFIG_MII                      1       /* MII PHY management */
408 #define CONFIG_FEC_AN_TIMEOUT           1
409 #define CONFIG_HAS_ETH0
410
411 /*
412  * Environment
413  */
414 #define CONFIG_ENV_IS_IN_FLASH  1
415 /* This has to be a multiple of the flash sector size */
416 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + \
417                                          CONFIG_SYS_MONITOR_LEN)
418 #define CONFIG_ENV_SIZE                 0x2000
419 #define CONFIG_ENV_SECT_SIZE            0x20000 /* one sector (256K) */
420
421 /* Address and size of Redundant Environment Sector     */
422 #define CONFIG_ENV_ADDR_REDUND          (CONFIG_ENV_ADDR + \
423                                          CONFIG_ENV_SECT_SIZE)
424 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
425
426 #define CONFIG_LOADS_ECHO               1
427 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1
428
429 #include <config_cmd_default.h>
430
431 #define CONFIG_CMD_ASKENV
432 #define CONFIG_CMD_DHCP
433 #define CONFIG_CMD_EEPROM
434 #undef CONFIG_CMD_FUSE
435 #define CONFIG_CMD_I2C
436 #undef CONFIG_CMD_IDE
437 #define CONFIG_CMD_JFFS2
438 #define CONFIG_CMD_MII
439 #define CONFIG_CMD_NFS
440 #define CONFIG_CMD_PING
441 #define CONFIG_CMD_REGINFO
442
443 #if defined(CONFIG_PCI)
444 #define CONFIG_CMD_PCI
445 #endif
446
447 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
448 #define CONFIG_DOS_PARTITION
449 #define CONFIG_MAC_PARTITION
450 #define CONFIG_ISO_PARTITION
451 #endif /* defined(CONFIG_CMD_IDE) */
452
453 /*
454  * Dynamic MTD partition support
455  */
456 #define CONFIG_CMD_MTDPARTS
457 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
458 #define CONFIG_FLASH_CFI_MTD
459 #define MTDIDS_DEFAULT          "nor0=f8000000.flash,nand0=mpc5121.nand"
460
461 /*
462  * NOR flash layout:
463  *
464  * F8000000 - FEAFFFFF  107 MiB         User Data
465  * FEB00000 - FFAFFFFF   16 MiB         Root File System
466  * FFB00000 - FFFEFFFF    4 MiB         Linux Kernel
467  * FFF00000 - FFFBFFFF  768 KiB         U-Boot (up to 512 KiB) and 2 x * env
468  * FFFC0000 - FFFFFFFF  256 KiB         Device Tree
469  *
470  * NAND flash layout: one big partition
471  */
472 #define MTDPARTS_DEFAULT        "mtdparts=f8000000.flash:107m(user),"   \
473                                                 "16m(rootfs),"          \
474                                                 "4m(kernel),"           \
475                                                 "768k(u-boot),"         \
476                                                 "256k(dtb);"            \
477                                         "mpc5121.nand:-(data)"
478
479 /*
480  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
481  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
482  * is set to 0xFFFF, watchdog timeouts after about 64s. For details
483  * refer to chapter 36 of the MPC5121e Reference Manual.
484  */
485 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
486 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
487
488  /*
489  * Miscellaneous configurable options
490  */
491 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
492 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
493 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
494
495 #ifdef CONFIG_CMD_KGDB
496 # define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
497 #else
498 # define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
499 #endif
500
501 /* Print Buffer Size */
502 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
503                                  sizeof(CONFIG_SYS_PROMPT) + 16)
504 /* max number of command args */
505 #define CONFIG_SYS_MAXARGS      32
506 /* Boot Argument Buffer Size */
507 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
508
509 #define CONFIG_SYS_HZ           1000
510
511 /*
512  * For booting Linux, the board info and command line data
513  * have to be in the first 8 MB of memory, since this is
514  * the maximum mapped by the Linux kernel during initialization.
515  */
516 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)
517
518 /* Cache Configuration */
519 #define CONFIG_SYS_DCACHE_SIZE          32768
520 #define CONFIG_SYS_CACHELINE_SIZE       32
521 #ifdef CONFIG_CMD_KGDB
522 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of 32 */
523 #endif
524
525 #define CONFIG_SYS_HID0_INIT            0x000000000
526 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
527                                          HID0_ICE)
528 #define CONFIG_SYS_HID2 HID2_HBE
529
530 #define CONFIG_HIGH_BATS                1       /* High BATs supported */
531
532 /*
533  * Internal Definitions
534  *
535  * Boot Flags
536  */
537 #define BOOTFLAG_COLD                   0x01
538 #define BOOTFLAG_WARM                   0x02
539
540 #ifdef CONFIG_CMD_KGDB
541 #define CONFIG_KGDB_BAUDRATE            230400  /* speed of kgdb serial port */
542 #define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
543 #endif
544
545 /*
546  * Environment Configuration
547  */
548 #define CONFIG_ENV_OVERWRITE
549 #define CONFIG_TIMESTAMP
550
551 #define CONFIG_HOSTNAME                 aria
552 #define CONFIG_BOOTFILE                 aria/uImage
553 #define CONFIG_ROOTPATH                 /opt/eldk/ppc_6xx
554
555 #define CONFIG_LOADADDR                 400000  /* default load addr */
556
557 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
558 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
559
560 #define CONFIG_BAUDRATE         115200
561
562 #define CONFIG_PREBOOT  "echo;" \
563         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
564         "echo"
565
566 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
567         "u-boot_addr_r=200000\0"                                        \
568         "kernel_addr_r=600000\0"                                        \
569         "fdt_addr_r=880000\0"                                           \
570         "ramdisk_addr_r=900000\0"                                       \
571         "u-boot_addr=FFF00000\0"                                        \
572         "kernel_addr=FFB00000\0"                                        \
573         "fdt_addr=FFFC0000\0"                                           \
574         "ramdisk_addr=FEB00000\0"                                       \
575         "ramdiskfile=aria/uRamdisk\0"                           \
576         "u-boot=aria/u-boot.bin\0"                                      \
577         "fdtfile=aria/aria.dtb\0"                                       \
578         "netdev=eth0\0"                                                 \
579         "consdev=ttyPSC0\0"                                             \
580         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
581                 "nfsroot=${serverip}:${rootpath}\0"                     \
582         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
583         "addip=setenv bootargs ${bootargs} "                            \
584                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
585                 ":${hostname}:${netdev}:off panic=1\0"                  \
586         "addtty=setenv bootargs ${bootargs} "                           \
587                 "console=${consdev},${baudrate}\0"                      \
588         "flash_nfs=run nfsargs addip addtty;"                           \
589                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
590         "flash_self=run ramargs addip addtty;"                          \
591                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
592         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
593                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
594                 "run nfsargs addip addtty;"                             \
595                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
596         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
597                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
598                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
599                 "run ramargs addip addtty;"                             \
600                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
601         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
602         "update=protect off ${u-boot_addr} +${filesize};"               \
603                 "era ${u-boot_addr} +${filesize};"                      \
604                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
605         "upd=run load update\0"                                         \
606         ""
607
608 #define CONFIG_BOOTCOMMAND      "run flash_self"
609
610 #define CONFIG_OF_LIBFDT        1
611 #define CONFIG_OF_BOARD_SETUP   1
612 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
613
614 #define OF_CPU                  "PowerPC,5121@0"
615 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
616 #define OF_TBCLK                (bd->bi_busfreq / 4)
617 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
618
619 /*-----------------------------------------------------------------------
620  * IDE/ATA stuff
621  *-----------------------------------------------------------------------
622  */
623
624 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
625 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
626 #undef  CONFIG_IDE_LED                  /* LED   for IDE not supported  */
627
628 #define CONFIG_IDE_RESET                /* reset for IDE supported      */
629 #define CONFIG_IDE_PREINIT
630
631 #define CONFIG_SYS_IDE_MAXBUS           1       /* 1 IDE bus            */
632 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* 1 drive per IDE bus  */
633
634 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
635 #define CONFIG_SYS_ATA_BASE_ADDR        get_pata_base()
636
637 /* Offset for data I/O                  RefMan MPC5121EE Table 28-10    */
638 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x00A0)
639
640 /* Offset for normal register accesses  */
641 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
642
643 /* Offset for alternate registers       RefMan MPC5121EE Table 28-23    */
644 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x00D8)
645
646 /* Interval between registers   */
647 #define CONFIG_SYS_ATA_STRIDE           4
648
649 #define ATA_BASE_ADDR                   get_pata_base()
650
651 /*
652  * Control register bit definitions
653  */
654 #define FSL_ATA_CTRL_FIFO_RST_B         0x80000000
655 #define FSL_ATA_CTRL_ATA_RST_B          0x40000000
656 #define FSL_ATA_CTRL_FIFO_TX_EN         0x20000000
657 #define FSL_ATA_CTRL_FIFO_RCV_EN        0x10000000
658 #define FSL_ATA_CTRL_DMA_PENDING        0x08000000
659 #define FSL_ATA_CTRL_DMA_ULTRA          0x04000000
660 #define FSL_ATA_CTRL_DMA_WRITE          0x02000000
661 #define FSL_ATA_CTRL_IORDY_EN           0x01000000
662
663 #endif  /* __CONFIG_H */