include/configs/aria.h

   1 /*
   2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
   3  * (C) Copyright 2009, DAVE Srl <www.dave.eu>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Aria board configuration file
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #define CONFIG_ARIA 1
  32 /*
  33  * Memory map for the ARIA board:
  34  *
  35  * 0x0000_0000-0x0FFF_FFFF      DDR RAM (256 MB)
  36  * 0x3000_0000-0x3001_FFFF      On Chip SRAM (128 KB)
  37  * 0x3010_0000-0x3011_FFFF      On Board SRAM (128 KB) - CS6
  38  * 0x3020_0000-0x3021_FFFF      FPGA (128 KB) - CS2
  39  * 0x8000_0000-0x803F_FFFF      IMMR (4 MB)
  40  * 0x8400_0000-0x82FF_FFFF      PCI I/O space (16 MB)
  41  * 0xA000_0000-0xAFFF_FFFF      PCI memory space (256 MB)
  42  * 0xB000_0000-0xBFFF_FFFF      PCI memory mapped I/O space (256 MB)
  43  * 0xFC00_0000-0xFFFF_FFFF      NOR Boot FLASH (64 MB)
  44  */
  45
  46 /*
  47  * High Level Configuration Options
  48  */
  49 #define CONFIG_E300             1       /* E300 Family */
  50 #define CONFIG_MPC512X          1       /* MPC512X family */
  51 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  52 #define CONFIG_FSL_DIU_LOGO_BMP 1       /* Don't include FSL DIU binary bmp */
  53
  54 /* video */
  55 #undef CONFIG_VIDEO
  56
  57 #if defined(CONFIG_VIDEO)
  58 #define CONFIG_CFB_CONSOLE
  59 #define CONFIG_VGA_AS_SINGLE_DEVICE
  60 #endif
  61
  62 /* CONFIG_PCI is defined at config time */
  63
  64 #define CONFIG_SYS_MPC512X_CLKIN        33000000        /* in Hz */
  65
  66 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
  67 #define CONFIG_MISC_INIT_R
  68
  69 #define CONFIG_SYS_IMMR                 0x80000000
  70 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR+0x2100)
  71
  72 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  73 #define CONFIG_SYS_MEMTEST_END          0x00400000
  74
  75 /*
  76  * DDR Setup - manually set all parameters as there's no SPD etc.
  77  */
  78 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  79 #define CONFIG_SYS_DDR_BASE             0x00000000
  80 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  81
  82 /* DDR Controller Configuration
  83  *
  84  * SYS_CFG:
  85  *      [31:31] MDDRC Soft Reset:       Diabled
  86  *      [30:30] DRAM CKE pin:           Enabled
  87  *      [29:29] DRAM CLK:               Enabled
  88  *      [28:28] Command Mode:           Enabled (For initialization only)
  89  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  90  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  91  *      [20:19] Read Test:              DON'T USE
  92  *      [18:18] Self Refresh:           Enabled
  93  *      [17:17] 16bit Mode:             Disabled
  94  *      [16:13] Ready Delay:            2
  95  *      [12:12] Half DQS Delay:         Disabled
  96  *      [11:11] Quarter DQS Delay:      Disabled
  97  *      [10:08] Write Delay:            2
  98  *      [07:07] Early ODT:              Disabled
  99  *      [06:06] On DIE Termination:     Disabled
 100  *      [05:05] FIFO Overflow Clear:    DON'T USE here
 101  *      [04:04] FIFO Underflow Clear:   DON'T USE here
 102  *      [03:03] FIFO Overflow Pending:  DON'T USE here
 103  *      [02:02] FIFO Underlfow Pending: DON'T USE here
 104  *      [01:01] FIFO Overlfow Enabled:  Enabled
 105  *      [00:00] FIFO Underflow Enabled: Enabled
 106  * TIME_CFG0
 107  *      [31:16] DRAM Refresh Time:      0 CSB clocks
 108  *      [15:8]  DRAM Command Time:      0 CSB clocks
 109  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 110  * TIME_CFG1
 111  *      [31:26] DRAM tRFC:
 112  *      [25:21] DRAM tWR1:
 113  *      [20:17] DRAM tWRT1:
 114  *      [16:11] DRAM tDRR:
 115  *      [10:05] DRAM tRC:
 116  *      [04:00] DRAM tRAS:
 117  * TIME_CFG2
 118  *      [31:28] DRAM tRCD:
 119  *      [27:23] DRAM tFAW:
 120  *      [22:19] DRAM tRTW1:
 121  *      [18:15] DRAM tCCD:
 122  *      [14:10] DRAM tRTP:
 123  *      [09:05] DRAM tRP:
 124  *      [04:00] DRAM tRPA
 125  */
 126 #define CONFIG_SYS_MDDRC_SYS_CFG     (  (1 << 31) |     /* RST_B */ \
 127                                         (1 << 30) |     /* CKE */ \
 128                                         (1 << 29) |     /* CLK_ON */ \
 129                                         (1 << 28) |     /* CMD_MODE */ \
 130                                         (4 << 25) |     /* DRAM_ROW_SELECT */ \
 131                                         (3 << 21) |     /* DRAM_BANK_SELECT */ \
 132                                         (0 << 18) |     /* SELF_REF_EN */ \
 133                                         (0 << 17) |     /* 16BIT_MODE */ \
 134                                         (2 << 13) |     /* RDLY */ \
 135                                         (0 << 12) |     /* HALF_DQS_DLY */ \
 136                                         (1 << 11) |     /* QUART_DQS_DLY */ \
 137                                         (2 <<  8) |     /* WDLY */ \
 138                                         (0 <<  7) |     /* EARLY_ODT */ \
 139                                         (1 <<  6) |     /* ON_DIE_TERMINATE */ \
 140                                         (0 <<  5) |     /* FIFO_OV_CLEAR */ \
 141                                         (0 <<  4) |     /* FIFO_UV_CLEAR */ \
 142                                         (0 <<  1) |     /* FIFO_OV_EN */ \
 143                                         (0 <<  0)       /* FIFO_UV_EN */ \
 144                                      )
 145
 146 #define CONFIG_SYS_MDDRC_SYS_CFG_RUN    (CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28))
 147 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x55D81189
 148 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34790863
 149
 150 #define CONFIG_SYS_MDDRC_SYS_CFG_EN     0xF0000000
 151 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x00003D2E
 152 #define CONFIG_SYS_MDDRC_TIME_CFG0_RUN  0x030C3D2E
 153
 154 #define CONFIG_SYS_MICRON_NOP           0x01380000
 155 #define CONFIG_SYS_MICRON_PCHG_ALL      0x01100400
 156 #define CONFIG_SYS_MICRON_EMR        (  (1 << 24) |     /* CMD_REQ */ \
 157                                         (0 << 22) |     /* DRAM_CS */ \
 158                                         (0 << 21) |     /* DRAM_RAS */ \
 159                                         (0 << 20) |     /* DRAM_CAS */ \
 160                                         (0 << 19) |     /* DRAM_WEB */ \
 161                                         (1 << 16) |     /* DRAM_BS[2:0] */ \
 162                                         (0 << 15) |     /* */ \
 163                                         (0 << 12) |     /* A12->out */ \
 164                                         (0 << 11) |     /* A11->RDQS */ \
 165                                         (0 << 10) |     /* A10->DQS# */ \
 166                                         (0 <<  7) |     /* OCD program */ \
 167                                         (0 <<  6) |     /* Rtt1 */ \
 168                                         (0 <<  3) |     /* posted CAS# */ \
 169                                         (0 <<  2) |     /* Rtt0 */ \
 170                                         (1 <<  1) |     /* ODS */ \
 171                                         (0 <<  0)       /* DLL */ \
 172                                      )
 173 #define CONFIG_SYS_MICRON_EMR2          0x01020000
 174 #define CONFIG_SYS_MICRON_EMR3          0x01030000
 175 #define CONFIG_SYS_MICRON_RFSH          0x01080000
 176 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
 177 #define CONFIG_SYS_MICRON_EMR_OCD    (  (1 << 24) |     /* CMD_REQ */ \
 178                                         (0 << 22) |     /* DRAM_CS */ \
 179                                         (0 << 21) |     /* DRAM_RAS */ \
 180                                         (0 << 20) |     /* DRAM_CAS */ \
 181                                         (0 << 19) |     /* DRAM_WEB */ \
 182                                         (1 << 16) |     /* DRAM_BS[2:0] */ \
 183                                         (0 << 15) |     /* */ \
 184                                         (0 << 12) |     /* A12->out */ \
 185                                         (0 << 11) |     /* A11->RDQS */ \
 186                                         (1 << 10) |     /* A10->DQS# */ \
 187                                         (7 <<  7) |     /* OCD program */ \
 188                                         (0 <<  6) |     /* Rtt1 */ \
 189                                         (0 <<  3) |     /* posted CAS# */ \
 190                                         (1 <<  2) |     /* Rtt0 */ \
 191                                         (0 <<  1) |     /* ODS (Output Drive Strength) */ \
 192                                         (0 <<  0)       /* DLL */ \
 193                                      )
 194
 195 /*
 196  * Backward compatible definitions,
 197  * so we do not have to change cpu/mpc512x/fixed_sdram.c
 198  */
 199 #define CONFIG_SYS_MICRON_EM2           (CONFIG_SYS_MICRON_EMR2)
 200 #define CONFIG_SYS_MICRON_EM3           (CONFIG_SYS_MICRON_EMR3)
 201 #define CONFIG_SYS_MICRON_EN_DLL        (CONFIG_SYS_MICRON_EMR)
 202 #define CONFIG_SYS_MICRON_OCD_DEFAULT   (CONFIG_SYS_MICRON_EMR_OCD)
 203
 204 /* DDR Priority Manager Configuration */
 205 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 206 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 207 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 208 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 209 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 210 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 211 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 212 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 213 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 214 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 215 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 216 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 217 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 218 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 219 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 220 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 221 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 222 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 223 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 224 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 225 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 226 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 227 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 228
 229 /*
 230  * NOR FLASH on the Local Bus
 231  */
 232 #define CONFIG_SYS_FLASH_CFI                            /* use the CFI code */
 233 #define CONFIG_FLASH_CFI_DRIVER                         /* use the CFI driver */
 234 #define CONFIG_SYS_FLASH_BASE           0xF8000000      /* start of FLASH */
 235 #define CONFIG_SYS_FLASH_SIZE           0x08000000      /* max flash size */
 236
 237 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 238 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 239 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 240 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* max sectors */
 241
 242 #undef CONFIG_SYS_FLASH_CHECKSUM
 243
 244 #define CONFIG_SYS_SRAM_BASE            0x30000000
 245 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 246
 247 /* Make two SRAM regions contiguous */
 248 #define CONFIG_SYS_ARIA_SRAM_BASE       (CONFIG_SYS_SRAM_BASE + \
 249                                          CONFIG_SYS_SRAM_SIZE)
 250 #define CONFIG_SYS_ARIA_SRAM_SIZE       0x00100000      /* reserve 1MB-window */
 251
 252 #define CONFIG_SYS_ARIA_FPGA_BASE       (CONFIG_SYS_ARIA_SRAM_BASE + \
 253                                          CONFIG_SYS_ARIA_SRAM_SIZE)
 254 #define CONFIG_SYS_ARIA_FPGA_SIZE       0x20000         /* 128 KB */
 255
 256 #define CONFIG_SYS_CS0_CFG              0x05059150
 257 #define CONFIG_SYS_CS2_CFG              (       (5 << 24) | \
 258                                                 (5 << 16) | \
 259                                                 (1 << 15) | \
 260                                                 (0 << 14) | \
 261                                                 (0 << 13) | \
 262                                                 (1 << 12) | \
 263                                                 (0 << 10) | \
 264                                                 (3 <<  8) | /* 32 bit */ \
 265                                                 (0 <<  7) | \
 266                                                 (1 <<  6) | \
 267                                                 (1 <<  4) | \
 268                                                 (0 <<  3) | \
 269                                                 (0 <<  2) | \
 270                                                 (0 <<  1) | \
 271                                                 (0 <<  0)   \
 272                                         )
 273 #define CONFIG_SYS_CS6_CFG              0x05059150
 274
 275 /* Use alternative CS timing for CS0 and CS2 */
 276 #define CONFIG_SYS_CS_ALETIMING 0x00000005
 277
 278 /* Use SRAM for initial stack */
 279 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE
 280 #define CONFIG_SYS_INIT_RAM_END         CONFIG_SYS_SRAM_SIZE
 281
 282 #define CONFIG_SYS_GBL_DATA_SIZE        0x100
 283 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - \
 284                                          CONFIG_SYS_GBL_DATA_SIZE)
 285 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 286
 287 #define CONFIG_SYS_MONITOR_BASE         TEXT_BASE
 288 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
 289
 290 #ifdef  CONFIG_FSL_DIU_FB
 291 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)
 292 #else
 293 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 294 #endif
 295
 296 /* FPGA */
 297 #define CONFIG_ARIA_FPGA                1
 298
 299 /*
 300  * Serial Port
 301  */
 302 #define CONFIG_CONS_INDEX               1
 303 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 304
 305 /*
 306  * Serial console configuration
 307  */
 308 #define CONFIG_PSC_CONSOLE              3       /* console on PSC3 */
 309 #if CONFIG_PSC_CONSOLE != 3
 310 #error CONFIG_PSC_CONSOLE must be 3
 311 #endif
 312
 313 #define CONFIG_BAUDRATE                 115200  /* ... at 115200 bps */
 314 #define CONFIG_SYS_BAUDRATE_TABLE  \
 315         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 316
 317 #define CONSOLE_FIFO_TX_SIZE            FIFOC_PSC3_TX_SIZE
 318 #define CONSOLE_FIFO_TX_ADDR            FIFOC_PSC3_TX_ADDR
 319 #define CONSOLE_FIFO_RX_SIZE            FIFOC_PSC3_RX_SIZE
 320 #define CONSOLE_FIFO_RX_ADDR            FIFOC_PSC3_RX_ADDR
 321
 322 #define CONFIG_CMDLINE_EDITING          1       /* command line history */
 323 /* Use the HUSH parser */
 324 #define CONFIG_SYS_HUSH_PARSER
 325 #ifdef  CONFIG_SYS_HUSH_PARSER
 326 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 327 #endif
 328
 329 /*
 330  * PCI
 331  */
 332 #ifdef CONFIG_PCI
 333
 334 #define CONFIG_SYS_PCI_MEM_BASE         0xA0000000
 335 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 336 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000      /* 256M */
 337 #define CONFIG_SYS_PCI_MMIO_BASE        (CONFIG_SYS_PCI_MEM_BASE + \
 338                                          CONFIG_SYS_PCI_MEM_SIZE)
 339 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 340 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000      /* 256M */
 341 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 342 #define CONFIG_SYS_PCI_IO_PHYS          0x84000000
 343 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000      /* 16M */
 344
 345 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 346
 347 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 348
 349 #endif
 350
 351 /* I2C */
 352 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 353 #undef CONFIG_SOFT_I2C                  /* so disable bit-banged I2C */
 354 #define CONFIG_I2C_MULTI_BUS
 355 #define CONFIG_I2C_CMD_TREE
 356
 357 /* I2C speed and slave address */
 358 #define CONFIG_SYS_I2C_SPEED            100000
 359 #define CONFIG_SYS_I2C_SLAVE            0x7F
 360 #if 0
 361 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 362 #endif
 363
 364 /*
 365  * IIM - IC Identification Module
 366  */
 367 #undef CONFIG_IIM
 368
 369 /*
 370  * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
 371  * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
 372  */
 373 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 374 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 375 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 376 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 377
 378 /*
 379  * Ethernet configuration
 380  */
 381 #define CONFIG_MPC512x_FEC              1
 382 #define CONFIG_NET_MULTI
 383 #define CONFIG_PHY_ADDR                 0x17
 384 #define CONFIG_MII                      1       /* MII PHY management */
 385 #define CONFIG_FEC_AN_TIMEOUT           1
 386 #define CONFIG_HAS_ETH0
 387
 388 /*
 389  * Environment
 390  */
 391 #define CONFIG_ENV_IS_IN_FLASH  1
 392 /* This has to be a multiple of the flash sector size */
 393 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + \
 394                                          CONFIG_SYS_MONITOR_LEN)
 395 #define CONFIG_ENV_SIZE                 0x2000
 396 #define CONFIG_ENV_SECT_SIZE            0x20000 /* one sector (256K) */
 397
 398 /* Address and size of Redundant Environment Sector     */
 399 #define CONFIG_ENV_ADDR_REDUND          (CONFIG_ENV_ADDR + \
 400                                          CONFIG_ENV_SECT_SIZE)
 401 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 402
 403 #define CONFIG_LOADS_ECHO               1
 404 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1
 405
 406 #include <config_cmd_default.h>
 407
 408 #define CONFIG_CMD_ASKENV
 409 #define CONFIG_CMD_DHCP
 410 #define CONFIG_CMD_EEPROM
 411 #undef CONFIG_CMD_FUSE
 412 #define CONFIG_CMD_I2C
 413 #undef CONFIG_CMD_IDE
 414 #define CONFIG_CMD_MII
 415 #define CONFIG_CMD_NFS
 416 #define CONFIG_CMD_PING
 417 #define CONFIG_CMD_REGINFO
 418
 419 #if defined(CONFIG_PCI)
 420 #define CONFIG_CMD_PCI
 421 #endif
 422
 423 #if defined(CONFIG_CMD_IDE)
 424 #define CONFIG_DOS_PARTITION
 425 #define CONFIG_MAC_PARTITION
 426 #define CONFIG_ISO_PARTITION
 427 #endif /* defined(CONFIG_CMD_IDE) */
 428
 429 /*
 430  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
 431  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
 432  * is set to 0xFFFF, watchdog timeouts after about 64s. For details
 433  * refer to chapter 36 of the MPC5121e Reference Manual.
 434  */
 435 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 436 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
 437
 438  /*
 439  * Miscellaneous configurable options
 440  */
 441 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 442 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 443 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 444
 445 #ifdef CONFIG_CMD_KGDB
 446 # define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
 447 #else
 448 # define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
 449 #endif
 450
 451 /* Print Buffer Size */
 452 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 453                                  sizeof(CONFIG_SYS_PROMPT) + 16)
 454 /* max number of command args */
 455 #define CONFIG_SYS_MAXARGS      32
 456 /* Boot Argument Buffer Size */
 457 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 458
 459 #define CONFIG_SYS_HZ           1000
 460
 461 /*
 462  * For booting Linux, the board info and command line data
 463  * have to be in the first 8 MB of memory, since this is
 464  * the maximum mapped by the Linux kernel during initialization.
 465  */
 466 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)
 467
 468 /* Cache Configuration */
 469 #define CONFIG_SYS_DCACHE_SIZE          32768
 470 #define CONFIG_SYS_CACHELINE_SIZE       32
 471 #ifdef CONFIG_CMD_KGDB
 472 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of 32 */
 473 #endif
 474
 475 #define CONFIG_SYS_HID0_INIT            0x000000000
 476 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 477                                          HID0_ICE)
 478 #define CONFIG_SYS_HID2 HID2_HBE
 479
 480 #define CONFIG_HIGH_BATS                1       /* High BATs supported */
 481
 482 /*
 483  * Internal Definitions
 484  *
 485  * Boot Flags
 486  */
 487 #define BOOTFLAG_COLD                   0x01
 488 #define BOOTFLAG_WARM                   0x02
 489
 490 #ifdef CONFIG_CMD_KGDB
 491 #define CONFIG_KGDB_BAUDRATE            230400  /* speed of kgdb serial port */
 492 #define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
 493 #endif
 494
 495 /*
 496  * Environment Configuration
 497  */
 498 #define CONFIG_ENV_OVERWRITE
 499 #define CONFIG_TIMESTAMP
 500
 501 #define CONFIG_HOSTNAME                 aria
 502 #define CONFIG_BOOTFILE                 aria/uImage
 503 #define CONFIG_ROOTPATH                 /opt/eldk/ppc_6xx
 504
 505 #define CONFIG_LOADADDR                 400000  /* default load addr */
 506
 507 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 508 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 509
 510 #define CONFIG_BAUDRATE         115200
 511
 512 #define CONFIG_PREBOOT  "echo;" \
 513         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 514         "echo"
 515
 516 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 517         "u-boot_addr_r=200000\0"                                        \
 518         "kernel_addr_r=600000\0"                                        \
 519         "fdt_addr_r=880000\0"                                           \
 520         "ramdisk_addr_r=900000\0"                                       \
 521         "u-boot_addr=FFF00000\0"                                        \
 522         "kernel_addr=FFC40000\0"                                        \
 523         "fdt_addr=FFEC0000\0"                                           \
 524         "ramdisk_addr=FC040000\0"                                       \
 525         "ramdiskfile=aria/uRamdisk\0"                           \
 526         "u-boot=aria/u-boot.bin\0"                                      \
 527         "fdtfile=aria/aria.dtb\0"                                       \
 528         "netdev=eth0\0"                                                 \
 529         "consdev=ttyPSC0\0"                                             \
 530         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 531                 "nfsroot=${serverip}:${rootpath}\0"                     \
 532         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 533         "addip=setenv bootargs ${bootargs} "                            \
 534                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 535                 ":${hostname}:${netdev}:off panic=1\0"                  \
 536         "addtty=setenv bootargs ${bootargs} "                           \
 537                 "console=${consdev},${baudrate}\0"                      \
 538         "flash_nfs=run nfsargs addip addtty;"                           \
 539                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 540         "flash_self=run ramargs addip addtty;"                          \
 541                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 542         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 543                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 544                 "run nfsargs addip addtty;"                             \
 545                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 546         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 547                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 548                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 549                 "run ramargs addip addtty;"                             \
 550                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 551         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 552         "update=protect off ${u-boot_addr} +${filesize};"               \
 553                 "era ${u-boot_addr} +${filesize};"                      \
 554                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 555         "upd=run load update\0"                                         \
 556         ""
 557
 558 #define CONFIG_BOOTCOMMAND      "run flash_self"
 559
 560 #define CONFIG_OF_LIBFDT        1
 561 #define CONFIG_OF_BOARD_SETUP   1
 562 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 563
 564 #define OF_CPU                  "PowerPC,5121@0"
 565 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 566 #define OF_TBCLK                (bd->bi_busfreq / 4)
 567 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 568
 569 /*-----------------------------------------------------------------------
 570  * IDE/ATA stuff
 571  *-----------------------------------------------------------------------
 572  */
 573
 574 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 575 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 576 #undef  CONFIG_IDE_LED                  /* LED   for IDE not supported  */
 577
 578 #define CONFIG_IDE_RESET                /* reset for IDE supported      */
 579 #define CONFIG_IDE_PREINIT
 580
 581 #define CONFIG_SYS_IDE_MAXBUS           1       /* 1 IDE bus            */
 582 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* 1 drive per IDE bus  */
 583
 584 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 585 #define CONFIG_SYS_ATA_BASE_ADDR        get_pata_base()
 586
 587 /* Offset for data I/O                  RefMan MPC5121EE Table 28-10    */
 588 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x00A0)
 589
 590 /* Offset for normal register accesses  */
 591 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 592
 593 /* Offset for alternate registers       RefMan MPC5121EE Table 28-23    */
 594 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x00D8)
 595
 596 /* Interval between registers   */
 597 #define CONFIG_SYS_ATA_STRIDE           4
 598
 599 #define ATA_BASE_ADDR                   get_pata_base()
 600
 601 /*
 602  * Control register bit definitions
 603  */
 604 #define FSL_ATA_CTRL_FIFO_RST_B         0x80000000
 605 #define FSL_ATA_CTRL_ATA_RST_B          0x40000000
 606 #define FSL_ATA_CTRL_FIFO_TX_EN         0x20000000
 607 #define FSL_ATA_CTRL_FIFO_RCV_EN        0x10000000
 608 #define FSL_ATA_CTRL_DMA_PENDING        0x08000000
 609 #define FSL_ATA_CTRL_DMA_ULTRA          0x04000000
 610 #define FSL_ATA_CTRL_DMA_WRITE          0x02000000
 611 #define FSL_ATA_CTRL_IORDY_EN           0x01000000
 612
 613 #endif  /* __CONFIG_H */