1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Configuration settings for the Armadeus Project motherboard APF27
6 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
12 #define CONFIG_ENV_VERSION 10
13 #define CONFIG_BOARD_NAME apf27
18 #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
19 #define CONFIG_MACH_TYPE 1698 /* APF27 */
22 * Enable the call to miscellaneous platform dependent initialization.
28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
29 #define CONFIG_SPL_MAX_SIZE 2048
31 /* NAND boot config */
32 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
33 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
34 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
35 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
40 #define CONFIG_BOOTP_BOOTFILESIZE
41 #define CONFIG_BOOTP_DNS2
43 #define CONFIG_HOSTNAME "apf27"
44 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
47 * Memory configurations
49 #define CONFIG_NR_DRAM_POPULATED 1
51 #define ACFG_SDRAM_MBYTE_SYZE 64
53 #define PHYS_SDRAM_1 0xA0000000
54 #define PHYS_SDRAM_2 0xB0000000
55 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
57 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
58 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
60 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
61 + PHYS_SDRAM_1_SIZE - 0x0100000)
66 #define ACFG_MONITOR_OFFSET 0x00000000
67 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
68 #define CONFIG_ENV_OVERWRITE
69 #define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
70 #define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
71 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
72 #define CONFIG_ENV_OFFSET_REDUND \
73 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
74 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
75 #define CONFIG_FIRMWARE_OFFSET 0x00200000
76 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
77 #define CONFIG_KERNEL_OFFSET 0x00300000
78 #define CONFIG_ROOTFS_OFFSET 0x00800000
81 * U-Boot general configurations
83 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
84 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
85 /* Boot argument buffer size */
86 #define CONFIG_PREBOOT "run check_flash check_env;"
91 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
92 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
93 #define CONFIG_INITRD_TAG /* send initrd params */
95 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
97 #define ACFG_CONSOLE_DEV ttySMX0
98 #define CONFIG_BOOTCOMMAND "run ubifsboot"
99 #define CONFIG_SYS_AUTOLOAD "no"
101 * Default load address for user programs and kernel
103 #define CONFIG_LOADADDR 0xA0000000
104 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
109 #define CONFIG_EXTRA_ENV_SETTINGS \
110 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
111 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
112 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
113 "partition=nand0,6\0" \
114 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
115 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
116 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
117 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
118 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
119 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
120 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
121 "kernel_addr_r=A0000000\0" \
122 "check_env=if test -n ${flash_env_version}; " \
123 "then env default env_version; " \
124 "else env set flash_env_version ${env_version}; env save; "\
126 "if itest ${flash_env_version} < ${env_version}; then " \
127 "echo \"*** Warning - Environment version" \
128 " change suggests: run flash_reset_env; reset\"; "\
129 "env default flash_reset_env; "\
131 "check_flash=nand lock; nand unlock ${env_addr}; \0" \
132 "flash_reset_env=env default -f -a; saveenv; run update_env;" \
133 "echo Flash environment variables erased!\0" \
134 "download_uboot=tftpboot ${loadaddr} ${board_name}" \
135 "-u-boot-with-spl.bin\0" \
136 "flash_uboot=nand unlock ${u-boot_addr} ;" \
137 "nand erase.part u-boot;" \
138 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
139 "then nand lock; nand unlock ${env_addr};" \
140 "echo Flashing of uboot succeed;" \
141 "else echo Flashing of uboot failed;" \
143 "update_uboot=run download_uboot flash_uboot\0" \
144 "download_env=tftpboot ${loadaddr} ${board_name}" \
145 "-u-boot-env.txt\0" \
146 "flash_env=env import -t ${loadaddr}; env save; \0" \
147 "update_env=run download_env flash_env\0" \
148 "update_all=run update_env update_uboot\0" \
149 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \
154 #define CONFIG_MXC_UART
155 #define CONFIG_MXC_UART_BASE UART1_BASE
165 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
166 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
167 #define CONFIG_SYS_MAX_NAND_DEVICE 1
169 #define CONFIG_MXC_NAND_HWECC
170 #define CONFIG_SYS_NAND_LARGEPAGE
171 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
172 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
173 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
174 CONFIG_SYS_NAND_PAGE_SIZE
175 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
176 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
177 #define NAND_MAX_CHIPS 1
179 #define CONFIG_FLASH_SHOW_PROGRESS 45
180 #define CONFIG_SYS_NAND_QUIET 1
183 * Partitions & Filsystems
187 * Ethernet (on SOC imx FEC)
189 #define CONFIG_FEC_MXC
190 #define CONFIG_FEC_MXC_PHYADDR 0x1f
195 #define CONFIG_FPGA_COUNT 1
196 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
197 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
198 #define CONFIG_SYS_FPGA_CHECK_CTRLC
199 #define CONFIG_SYS_FPGA_CHECK_ERROR
204 #ifdef CONFIG_CMD_IMX_FUSE
205 #define IIM_MAC_BANK 0
206 #define IIM_MAC_ROW 5
207 #define IIM0_SCC_KEY 11
215 #ifdef CONFIG_CMD_I2C
216 #define CONFIG_SYS_I2C
217 #define CONFIG_SYS_I2C_MXC
218 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
219 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
220 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
221 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
222 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
223 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
224 #define CONFIG_SYS_I2C_NOPROBES { }
226 #ifdef CONFIG_CMD_EEPROM
227 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
228 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
231 #endif /* CONFIG_CMD_EEPROM */
232 #endif /* CONFIG_CMD_I2C */
237 #ifdef CONFIG_CMD_MMC
238 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000
244 #ifdef CONFIG_CMD_DATE
245 #define CONFIG_RTC_DS1374
246 #define CONFIG_SYS_RTC_BUS_NUM 0
247 #endif /* CONFIG_CMD_DATE */
252 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
253 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
255 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
257 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
259 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
260 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
263 #if (ACFG_SDRAM_MBYTE_SYZE == 128)
265 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
266 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
269 #if (ACFG_SDRAM_MBYTE_SYZE == 256)
271 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
272 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
275 #endif /* __CONFIG_H */