2 * Configuation settings for the Alpha Project AP-SH4A-4A board
4 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #define __AP_SH4A_4A_H
14 #define CONFIG_CPU_SH7734 1
15 #define CONFIG_AP_SH4A_4A 1
16 #define CONFIG_400MHZ_MODE 1
17 /* #define CONFIG_533MHZ_MODE 1 */
19 #define CONFIG_BOARD_LATE_INIT
20 #define CONFIG_SYS_TEXT_BASE 0x8BFC0000
22 #define CONFIG_CMD_FLASH
23 #define CONFIG_CMD_MEMORY
24 #define CONFIG_CMD_NET
25 #define CONFIG_CMD_PING
26 #define CONFIG_CMD_MII
27 #define CONFIG_CMD_NFS
28 #define CONFIG_CMD_SDRAM
29 #define CONFIG_CMD_ENV
30 #define CONFIG_CMD_SAVEENV
32 #define CONFIG_BAUDRATE 115200
33 #define CONFIG_BOOTDELAY 3
34 #define CONFIG_BOOTARGS "console=ttySC4,115200"
36 #define CONFIG_VERSION_VARIABLE
37 #undef CONFIG_SHOW_BOOT_PROGRESS
40 #define CONFIG_SH_ETHER 1
41 #define CONFIG_SH_ETHER_USE_PORT (0)
42 #define CONFIG_SH_ETHER_PHY_ADDR (0x0)
43 #define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII)
44 #define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */
46 #define CONFIG_PHY_MICREL 1
47 #define CONFIG_BITBANGMII
48 #define CONFIG_BITBANGMII_MULTI
51 #define CONFIG_CMD_I2C
52 #define CONFIG_SH_SH7734_I2C 1
53 #define CONFIG_HARD_I2C 1
54 #define CONFIG_I2C_MULTI_BUS 1
55 #define CONFIG_SYS_MAX_I2C_BUS 2
56 #define CONFIG_SYS_I2C_MODULE 0
57 #define CONFIG_SYS_I2C_SPEED 400000 /* 400 kHz */
58 #define CONFIG_SYS_I2C_SLAVE 0x50
59 #define CONFIG_SH_I2C_DATA_HIGH 4
60 #define CONFIG_SH_I2C_DATA_LOW 5
61 #define CONFIG_SH_I2C_CLOCK 500000000
62 #define CONFIG_SH_I2C_BASE0 0xFFC70000
63 #define CONFIG_SH_I2C_BASE1 0xFFC71000
65 /* undef to save memory */
66 #define CONFIG_SYS_LONGHELP
67 /* Monitor Command Prompt */
68 /* Buffer size for input from the Console */
69 #define CONFIG_SYS_CBSIZE 256
70 /* Buffer size for Console output */
71 #define CONFIG_SYS_PBSIZE 256
72 /* max args accepted for monitor commands */
73 #define CONFIG_SYS_MAXARGS 16
74 /* Buffer size for Boot Arguments passed to kernel */
75 #define CONFIG_SYS_BARGSIZE 512
76 /* List of legal baudrate settings for this board */
77 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
80 #define CONFIG_SCIF_CONSOLE 1
82 #define CONFIG_CONS_SCIF4 1
84 /* Suppress display of console information at boot */
85 #undef CONFIG_SYS_CONSOLE_INFO_QUIET
86 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
87 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
90 #define CONFIG_SYS_SDRAM_BASE (0x88000000)
91 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
92 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
94 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
95 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE)
96 /* Enable alternate, more extensive, memory test */
97 #undef CONFIG_SYS_ALT_MEMTEST
98 /* Scratch address used by the alternate memory test */
99 #undef CONFIG_SYS_MEMTEST_SCRATCH
101 /* Enable temporary baudrate change while serial download */
102 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
105 #define CONFIG_FLASH_CFI_DRIVER 1
106 #define CONFIG_SYS_FLASH_CFI
107 #undef CONFIG_SYS_FLASH_QUIET_TEST
108 #define CONFIG_SYS_FLASH_EMPTY_INFO
109 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
110 #define CONFIG_SYS_MAX_FLASH_SECT 512
112 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
113 #define CONFIG_SYS_MAX_FLASH_BANKS 1
114 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
116 /* Timeout for Flash erase operations (in ms) */
117 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
118 /* Timeout for Flash write operations (in ms) */
119 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
120 /* Timeout for Flash set sector lock bit operations (in ms) */
121 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
122 /* Timeout for Flash clear lock bit operations (in ms) */
123 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
126 * Use hardware flash sectors protection instead
127 * of U-Boot software protection
129 #undef CONFIG_SYS_FLASH_PROTECTION
130 #undef CONFIG_SYS_DIRECT_FLASH_TFTP
132 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
133 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
135 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
136 /* Size of DRAM reserved for malloc() use */
137 #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
138 /* size in bytes reserved for initial data */
139 #define CONFIG_SYS_GBL_DATA_SIZE (256)
140 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
143 #define CONFIG_ENV_IS_IN_FLASH
144 #define CONFIG_ENV_OVERWRITE 1
145 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
146 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
147 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
148 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
149 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
150 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
153 #if defined(CONFIG_400MHZ_MODE)
154 #define CONFIG_SYS_CLK_FREQ 50000000
156 #define CONFIG_SYS_CLK_FREQ 44444444
158 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
159 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
160 #define CONFIG_SYS_TMU_CLK_DIV 4
162 #endif /* __AP_SH4A_4A_H */