1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Sysam AMCORE board configuration
5 * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
8 #ifndef __AMCORE_CONFIG_H
9 #define __AMCORE_CONFIG_H
11 #define CONFIG_HOSTNAME "AMCORE"
14 #define CONFIG_MCFUART
15 #define CONFIG_SYS_UART_PORT 0
17 #define CONFIG_BOOTCOMMAND "bootm ffc20000"
18 #define CONFIG_EXTRA_ENV_SETTINGS \
19 "upgrade_uboot=loady; " \
20 "protect off 0xffc00000 0xffc1ffff; " \
21 "erase 0xffc00000 0xffc1ffff; " \
22 "cp.b 0x20000 0xffc00000 ${filesize}\0" \
23 "upgrade_kernel=loady; " \
24 "erase 0xffc20000 0xffefffff; " \
25 "cp.b 0x20000 0xffc20000 ${filesize}\0" \
26 "upgrade_jffs2=loady; " \
27 "erase 0xfff00000 0xffffffff; " \
28 "cp.b 0x20000 0xfff00000 ${filesize}\0"
30 #define CONFIG_SYS_HZ 1000
32 #define CONFIG_SYS_CLK 45000000
33 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
34 /* Register Base Addrs */
35 #define CONFIG_SYS_MBAR 0x10000000
36 /* Definitions for initial stack pointer and data area (in DPRAM) */
37 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
38 /* size of internal SRAM */
39 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
40 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
41 GENERATED_GBL_DATA_SIZE)
42 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
44 #define CONFIG_SYS_SDRAM_BASE 0x00000000
45 #define CONFIG_SYS_SDRAM_SIZE 0x1000000
46 #define CONFIG_SYS_FLASH_BASE 0xffc00000
47 #define CONFIG_SYS_MAX_FLASH_BANKS 1
48 #define CONFIG_SYS_MAX_FLASH_SECT 1024
49 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
51 /* amcore design has flash data bytes wired swapped */
52 #define CONFIG_SYS_WRITE_SWAPPED_DATA
54 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
55 #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
56 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
58 #define LDS_BOARD_TEXT \
59 . = DEFINED(env_offset) ? env_offset : .; \
60 env/embedded.o(.text*);
62 /* memory map space for linux boot data */
63 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
68 * Special 8K version 3 core cache.
69 * This is a single unified instruction/data cache.
70 * sdram - single region - no masks
73 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
74 CONFIG_SYS_INIT_RAM_SIZE - 8)
75 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
76 CONFIG_SYS_INIT_RAM_SIZE - 4)
77 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
78 #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
80 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
83 /* CS0 - AMD Flash, address 0xffc00000 */
84 #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
85 /* 4MB, AA=0,V=1 C/I BIT for errata */
86 #define CONFIG_SYS_CS0_MASK 0x003f0001
87 /* WS=10, AA=1, PS=16bit (10) */
88 #define CONFIG_SYS_CS0_CTRL 0x1980
89 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
90 #define CONFIG_SYS_CS1_BASE 0x3000
91 #define CONFIG_SYS_CS1_MASK 0x00070001
92 #define CONFIG_SYS_CS1_CTRL 0x0100
94 #endif /* __AMCORE_CONFIG_H */