include/configs/amcore.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Sysam AMCORE board configuration
   4  *
   5  * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
   6  */
   7
   8 #ifndef __AMCORE_CONFIG_H
   9 #define __AMCORE_CONFIG_H
  10
  11 #define CFG_SYS_UART_PORT               0
  12
  13 #define CFG_MCFTMR
  14 #define CFG_SYS_UART_PORT               0
  15 #define CFG_SYS_BAUDRATE_TABLE          { 9600, 19200, 38400, 57600, 115200 }
  16
  17 #define CFG_EXTRA_ENV_SETTINGS                                  \
  18         "upgrade_uboot=loady; "                                 \
  19                 "protect off 0xffc00000 0xffc2ffff; "           \
  20                 "erase 0xffc00000 0xffc2ffff; "                 \
  21                 "cp.b 0x20000 0xffc00000 ${filesize}\0"         \
  22         "upgrade_kernel=loady; "                                \
  23                 "erase 0xffc30000 0xffefffff; "                 \
  24                 "cp.b 0x20000 0xffc30000 ${filesize}\0"         \
  25         "upgrade_jffs2=loady; "                                 \
  26                 "erase 0xfff00000 0xffffffff; "                 \
  27                 "cp.b 0x20000 0xfff00000 ${filesize}\0"
  28
  29 #define CFG_SYS_CLK                     45000000
  30 #define CFG_SYS_CPU_CLK         (CFG_SYS_CLK * 2)
  31 /* Register Base Addrs */
  32 #define CFG_SYS_MBAR                    0x10000000
  33 /* Definitions for initial stack pointer and data area (in DPRAM) */
  34 #define CFG_SYS_INIT_RAM_ADDR   0x20000000
  35 /* size of internal SRAM */
  36 #define CFG_SYS_INIT_RAM_SIZE   0x1000
  37
  38 #define CFG_SYS_SDRAM_BASE              0x00000000
  39 #define CFG_SYS_SDRAM_SIZE              0x1000000
  40 #define CFG_SYS_FLASH_BASE              0xffc00000
  41
  42 /* amcore design has flash data bytes wired swapped */
  43 #define CFG_SYS_WRITE_SWAPPED_DATA
  44
  45 #define LDS_BOARD_TEXT \
  46         . = DEFINED(env_offset) ? env_offset : .; \
  47         env/embedded.o(.text*);
  48
  49 /* memory map space for linux boot data */
  50 #define CFG_SYS_BOOTMAPSZ               (8 << 20)
  51
  52 /*
  53  * Cache Configuration
  54  *
  55  * Special 8K version 3 core cache.
  56  * This is a single unified instruction/data cache.
  57  * sdram - single region - no masks
  58  */
  59
  60 #define ICACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
  61                                          CFG_SYS_INIT_RAM_SIZE - 8)
  62 #define DCACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
  63                                          CFG_SYS_INIT_RAM_SIZE - 4)
  64 #define CFG_SYS_ICACHE_INV           (CF_CACR_CINVA)
  65 #define CFG_SYS_CACHE_ACR0              (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
  66                                          CF_ACR_EN)
  67 #define CFG_SYS_CACHE_ICACR             (CF_CACR_DCM_P | CF_CACR_ESB | \
  68                                          CF_CACR_EC)
  69
  70 /* CS0 - AMD Flash, address 0xffc00000 */
  71 #define CFG_SYS_CS0_BASE                (CFG_SYS_FLASH_BASE>>16)
  72 /* 4MB, AA=0,V=1  C/I BIT for errata */
  73 #define CFG_SYS_CS0_MASK                0x003f0001
  74 /* WS=10, AA=1, PS=16bit (10) */
  75 #define CFG_SYS_CS0_CTRL                0x1980
  76 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
  77 #define CFG_SYS_CS1_BASE                0x3000
  78 #define CFG_SYS_CS1_MASK                0x00070001
  79 #define CFG_SYS_CS1_CTRL                0x0100
  80
  81 #endif  /* __AMCORE_CONFIG_H */