2 * Sysam AMCORE board configuration
4 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __AMCORE_CONFIG_H
10 #define __AMCORE_CONFIG_H
13 #define CONFIG_HOSTNAME AMCORE
16 #define CONFIG_MCFUART
17 #define CONFIG_SYS_UART_PORT 0
18 #define CONFIG_BAUDRATE 115200
19 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
21 #define CONFIG_BOOTCOMMAND "bootm ffc20000"
24 #define CONFIG_CMD_DIAG
26 /* undef to save memory */
27 #undef CONFIG_SYS_LONGHELP
29 #if defined(CONFIG_CMD_KGDB)
30 /* Console I/O buff. size */
31 #define CONFIG_SYS_CBSIZE 1024
33 #define CONFIG_SYS_CBSIZE 256
35 /* Print buffer size */
36 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
37 sizeof(CONFIG_SYS_PROMPT)+16)
38 /* max number of command args */
39 #define CONFIG_SYS_MAXARGS 16
40 /* Boot argument buffer size */
41 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
43 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */
44 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
45 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
47 #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
49 #define CONFIG_SYS_MEMTEST_START 0x0
50 #define CONFIG_SYS_MEMTEST_END 0x1000000
52 #define CONFIG_SYS_HZ 1000
54 #define CONFIG_SYS_CLK 45000000
55 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
56 /* Register Base Addrs */
57 #define CONFIG_SYS_MBAR 0x10000000
58 /* Definitions for initial stack pointer and data area (in DPRAM) */
59 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
60 /* size of internal SRAM */
61 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
62 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
63 GENERATED_GBL_DATA_SIZE)
64 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
66 #define CONFIG_SYS_SDRAM_BASE 0x00000000
67 #define CONFIG_SYS_SDRAM_SIZE 0x1000000
68 #define CONFIG_SYS_FLASH_BASE 0xffc00000
69 #define CONFIG_SYS_MAX_FLASH_BANKS 1
70 #define CONFIG_SYS_MAX_FLASH_SECT 1024
71 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
73 #define CONFIG_SYS_FLASH_CFI
74 #define CONFIG_FLASH_CFI_DRIVER
75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
76 /* amcore design has flash data bytes wired swapped */
77 #define CONFIG_SYS_WRITE_SWAPPED_DATA
79 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
80 #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
81 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
82 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
84 #define CONFIG_ENV_IS_IN_FLASH 1
85 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
86 CONFIG_SYS_MONITOR_LEN)
87 #define CONFIG_ENV_SIZE 0x1000
88 #define CONFIG_ENV_SECT_SIZE 0x1000
90 #define LDS_BOARD_TEXT \
91 . = DEFINED(env_offset) ? env_offset : .; \
92 common/env_embedded.o (.text*);
94 /* memory map space for linux boot data */
95 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
100 * Special 8K version 3 core cache.
101 * This is a single unified instruction/data cache.
102 * sdram - single region - no masks
104 #define CONFIG_SYS_CACHELINE_SIZE 16
106 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
107 CONFIG_SYS_INIT_RAM_SIZE - 8)
108 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
109 CONFIG_SYS_INIT_RAM_SIZE - 4)
110 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
111 #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
113 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
116 /* CS0 - AMD Flash, address 0xffc00000 */
117 #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
118 /* 4MB, AA=0,V=1 C/I BIT for errata */
119 #define CONFIG_SYS_CS0_MASK 0x003f0001
120 /* WS=10, AA=1, PS=16bit (10) */
121 #define CONFIG_SYS_CS0_CTRL 0x1980
122 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
123 #define CONFIG_SYS_CS1_BASE 0x3000
124 #define CONFIG_SYS_CS1_MASK 0x00070001
125 #define CONFIG_SYS_CS1_CTRL 0x0100
127 #endif /* __AMCORE_CONFIG_H */