include/configs/am3517_crane.h

   1 /*
   2  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
   3  *
   4  * Author: Srinath.R <srinath@mistralsolutions.com>
   5  *
   6  * Based on include/configs/am3517evm.h
   7  *
   8  * Copyright (C) 2011 Mistral Solutions pvt Ltd
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19
  20 #include <asm/arch/cpu.h>               /* get chip and board defs */
  21 #include <asm/arch/omap.h>
  22
  23 /* Clock Defines */
  24 #define V_OSCK                  26000000        /* Clock output from T2 */
  25 #define V_SCLK                  (V_OSCK >> 1)
  26
  27 #define CONFIG_MISC_INIT_R
  28
  29 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  30 #define CONFIG_SETUP_MEMORY_TAGS        1
  31 #define CONFIG_INITRD_TAG               1
  32 #define CONFIG_REVISION_TAG             1
  33
  34 /*
  35  * Size of malloc() pool
  36  */
  37 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  38 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  39                                                 /* initial data */
  40 /*
  41  * DDR related
  42  */
  43 #define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
  44
  45 /*
  46  * Hardware drivers
  47  */
  48
  49 /*
  50  * NS16550 Configuration
  51  */
  52 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  53
  54 #define CONFIG_SYS_NS16550_SERIAL
  55 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  56 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  57
  58 /*
  59  * select serial console configuration
  60  */
  61 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  62 #define CONFIG_SERIAL3                  3       /* UART3 on CRANEBOARD */
  63
  64 /* allow to overwrite serial and ethaddr */
  65 #define CONFIG_ENV_OVERWRITE
  66 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  67                                         115200}
  68
  69 /*
  70  * USB configuration
  71  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
  72  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
  73  */
  74
  75 #ifdef CONFIG_USB_AM35X
  76
  77 #ifdef CONFIG_USB_MUSB_HCD
  78
  79 #ifdef CONFIG_USB_KEYBOARD
  80 #define CONFIG_PREBOOT "usb start"
  81 #endif /* CONFIG_USB_KEYBOARD */
  82
  83 #endif /* CONFIG_USB_MUSB_HCD */
  84
  85 #ifdef CONFIG_USB_MUSB_UDC
  86 /* USB device configuration */
  87 #define CONFIG_USB_DEVICE               1
  88 #define CONFIG_USB_TTY                  1
  89 /* Change these to suit your needs */
  90 #define CONFIG_USBD_VENDORID            0x0451
  91 #define CONFIG_USBD_PRODUCTID           0x5678
  92 #define CONFIG_USBD_MANUFACTURER        "Texas Instruments"
  93 #define CONFIG_USBD_PRODUCT_NAME        "AM3517CRANE"
  94 #endif /* CONFIG_USB_MUSB_UDC */
  95
  96 #endif /* CONFIG_USB_AM35X */
  97
  98 #define CONFIG_SYS_I2C
  99
 100 /*
 101  * Board NAND Info.
 102  */
 103 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 104                                                         /* to access nand */
 105 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 106                                                         /* to access */
 107                                                         /* nand at CS0 */
 108
 109 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of */
 110                                                         /* NAND devices */
 111
 112 #define CONFIG_JFFS2_NAND
 113 /* nand device jffs2 lives on */
 114 #define CONFIG_JFFS2_DEV                "nand0"
 115 /* start of jffs2 partition */
 116 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 117 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* sz of jffs2 part */
 118
 119 /* Environment information */
 120
 121 #define CONFIG_BOOTFILE         "uImage"
 122
 123 #define CONFIG_EXTRA_ENV_SETTINGS \
 124         "loadaddr=0x82000000\0" \
 125         "console=ttyS2,115200n8\0" \
 126         "mmcdev=0\0" \
 127         "mmcargs=setenv bootargs console=${console} " \
 128                 "root=/dev/mmcblk0p2 rw " \
 129                 "rootfstype=ext3 rootwait\0" \
 130         "nandargs=setenv bootargs console=${console} " \
 131                 "root=/dev/mtdblock4 rw " \
 132                 "rootfstype=jffs2\0" \
 133         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 134         "bootscript=echo Running bootscript from mmc ...; " \
 135                 "source ${loadaddr}\0" \
 136         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 137         "mmcboot=echo Booting from mmc ...; " \
 138                 "run mmcargs; " \
 139                 "bootm ${loadaddr}\0" \
 140         "nandboot=echo Booting from nand ...; " \
 141                 "run nandargs; " \
 142                 "nand read ${loadaddr} 280000 400000; " \
 143                 "bootm ${loadaddr}\0" \
 144
 145 #define CONFIG_BOOTCOMMAND \
 146         "mmc dev ${mmcdev}; if mmc rescan; then " \
 147                 "if run loadbootscript; then " \
 148                         "run bootscript; " \
 149                 "else " \
 150                         "if run loaduimage; then " \
 151                                 "run mmcboot; " \
 152                         "else run nandboot; " \
 153                         "fi; " \
 154                 "fi; " \
 155         "else run nandboot; fi"
 156
 157 /*
 158  * Miscellaneous configurable options
 159  */
 160 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 161 #define CONFIG_SYS_MAXARGS              32      /* max number of command */
 162                                                 /* args */
 163 /* memtest works on */
 164 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 165 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 166                                         0x01F00000) /* 31MB */
 167
 168 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 169                                                                 /* address */
 170
 171 /*
 172  * AM3517 has 12 GP timers, they can be driven by the system clock
 173  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 174  * This rate is divided by a local divisor.
 175  */
 176 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 177 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 178
 179 /*-----------------------------------------------------------------------
 180  * Physical Memory Map
 181  */
 182 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 183 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 184 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 185
 186 /*-----------------------------------------------------------------------
 187  * FLASH and environment organization
 188  */
 189
 190 /* **** PISMO SUPPORT *** */
 191 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors */
 192                                                 /* on one chip */
 193 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 194 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 195
 196 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 197
 198 /* Monitor at start of flash */
 199 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 200
 201 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB sector */
 202 #define CONFIG_ENV_OFFSET               0x260000
 203 #define CONFIG_ENV_ADDR                 0x260000
 204
 205 /*-----------------------------------------------------------------------
 206  * CFI FLASH driver setup
 207  */
 208 /* timeout values are in ticks */
 209 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 210 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 211
 212 /* Flash banks JFFS2 should use */
 213 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 214                                         CONFIG_SYS_MAX_NAND_DEVICE)
 215 #define CONFIG_SYS_JFFS2_MEM_NAND
 216 /* use flash_info[2] */
 217 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 218 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 219
 220 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 221 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 222 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 223 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 224                                          CONFIG_SYS_INIT_RAM_SIZE - \
 225                                          GENERATED_GBL_DATA_SIZE)
 226
 227 /* Defines for SPL */
 228 #define CONFIG_SPL_TEXT_BASE            0x40200800
 229 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 230                                          CONFIG_SPL_TEXT_BASE)
 231
 232 #define CONFIG_SPL_BSS_START_ADDR       0x80000000
 233 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 234
 235 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 236 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 237
 238 #define CONFIG_SPL_NAND_BASE
 239 #define CONFIG_SPL_NAND_DRIVERS
 240 #define CONFIG_SPL_NAND_ECC
 241
 242 /* NAND boot config */
 243 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 244 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 245 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 246 #define CONFIG_SYS_NAND_OOBSIZE         64
 247 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 248 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 249 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 250                                                 10, 11, 12, 13}
 251 #define CONFIG_SYS_NAND_ECCSIZE         512
 252 #define CONFIG_SYS_NAND_ECCBYTES        3
 253 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 254 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 255 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 256
 257 /*
 258  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 259  * 64 bytes before this address should be set aside for u-boot.img's
 260  * header. That is 0x800FFFC0--0x80100000 should not be used for any
 261  * other needs.
 262  */
 263 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 264 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 265
 266 #endif /* __CONFIG_H */