include/configs/am3517_crane.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
   4  *
   5  * Author: Srinath.R <srinath@mistralsolutions.com>
   6  *
   7  * Based on include/configs/am3517evm.h
   8  *
   9  * Copyright (C) 2011 Mistral Solutions pvt Ltd
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18
  19 #include <asm/arch/cpu.h>               /* get chip and board defs */
  20 #include <asm/arch/omap.h>
  21
  22 /* Clock Defines */
  23 #define V_OSCK                  26000000        /* Clock output from T2 */
  24 #define V_SCLK                  (V_OSCK >> 1)
  25
  26 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  27 #define CONFIG_SETUP_MEMORY_TAGS        1
  28 #define CONFIG_INITRD_TAG               1
  29 #define CONFIG_REVISION_TAG             1
  30
  31 /*
  32  * Size of malloc() pool
  33  */
  34 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  35                                                 /* initial data */
  36 /*
  37  * DDR related
  38  */
  39 #define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
  40
  41 /*
  42  * Hardware drivers
  43  */
  44
  45 /*
  46  * NS16550 Configuration
  47  */
  48 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  49
  50 #define CONFIG_SYS_NS16550_SERIAL
  51 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  52 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  53
  54 /*
  55  * select serial console configuration
  56  */
  57 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  58
  59 /* allow to overwrite serial and ethaddr */
  60 #define CONFIG_ENV_OVERWRITE
  61 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  62                                         115200}
  63
  64 /*
  65  * USB configuration
  66  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
  67  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
  68  */
  69
  70 #ifdef CONFIG_USB_AM35X
  71 #ifdef CONFIG_USB_MUSB_UDC
  72 /* USB device configuration */
  73 #define CONFIG_USB_DEVICE               1
  74 #define CONFIG_USB_TTY                  1
  75 /* Change these to suit your needs */
  76 #define CONFIG_USBD_VENDORID            0x0451
  77 #define CONFIG_USBD_PRODUCTID           0x5678
  78 #define CONFIG_USBD_MANUFACTURER        "Texas Instruments"
  79 #define CONFIG_USBD_PRODUCT_NAME        "AM3517CRANE"
  80 #endif /* CONFIG_USB_MUSB_UDC */
  81
  82 #endif /* CONFIG_USB_AM35X */
  83
  84 #define CONFIG_SYS_I2C
  85
  86 /*
  87  * Board NAND Info.
  88  */
  89 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
  90                                                         /* to access */
  91                                                         /* nand at CS0 */
  92
  93 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of */
  94                                                         /* NAND devices */
  95
  96 #define CONFIG_JFFS2_NAND
  97 /* nand device jffs2 lives on */
  98 #define CONFIG_JFFS2_DEV                "nand0"
  99 /* start of jffs2 partition */
 100 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 101 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* sz of jffs2 part */
 102
 103 /* Environment information */
 104
 105 #define CONFIG_BOOTFILE         "uImage"
 106
 107 #define CONFIG_EXTRA_ENV_SETTINGS \
 108         "loadaddr=0x82000000\0" \
 109         "console=ttyS2,115200n8\0" \
 110         "mmcdev=0\0" \
 111         "mmcargs=setenv bootargs console=${console} " \
 112                 "root=/dev/mmcblk0p2 rw " \
 113                 "rootfstype=ext3 rootwait\0" \
 114         "nandargs=setenv bootargs console=${console} " \
 115                 "root=/dev/mtdblock4 rw " \
 116                 "rootfstype=jffs2\0" \
 117         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 118         "bootscript=echo Running bootscript from mmc ...; " \
 119                 "source ${loadaddr}\0" \
 120         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 121         "mmcboot=echo Booting from mmc ...; " \
 122                 "run mmcargs; " \
 123                 "bootm ${loadaddr}\0" \
 124         "nandboot=echo Booting from nand ...; " \
 125                 "run nandargs; " \
 126                 "nand read ${loadaddr} 280000 400000; " \
 127                 "bootm ${loadaddr}\0" \
 128
 129 #define CONFIG_BOOTCOMMAND \
 130         "mmc dev ${mmcdev}; if mmc rescan; then " \
 131                 "if run loadbootscript; then " \
 132                         "run bootscript; " \
 133                 "else " \
 134                         "if run loaduimage; then " \
 135                                 "run mmcboot; " \
 136                         "else run nandboot; " \
 137                         "fi; " \
 138                 "fi; " \
 139         "else run nandboot; fi"
 140
 141 /*
 142  * Miscellaneous configurable options
 143  */
 144 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 145 #define CONFIG_SYS_MAXARGS              32      /* max number of command */
 146                                                 /* args */
 147 /* memtest works on */
 148 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 149 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 150                                         0x01F00000) /* 31MB */
 151
 152 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 153                                                                 /* address */
 154
 155 /*
 156  * AM3517 has 12 GP timers, they can be driven by the system clock
 157  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 158  * This rate is divided by a local divisor.
 159  */
 160 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 161 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 162
 163 /*-----------------------------------------------------------------------
 164  * Physical Memory Map
 165  */
 166 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 167 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 168
 169 /*-----------------------------------------------------------------------
 170  * FLASH and environment organization
 171  */
 172
 173 /* **** PISMO SUPPORT *** */
 174 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors */
 175                                                 /* on one chip */
 176 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 177 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 178
 179 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 180
 181 /* Monitor at start of flash */
 182 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 183
 184 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB sector */
 185
 186 /*-----------------------------------------------------------------------
 187  * CFI FLASH driver setup
 188  */
 189 /* timeout values are in ticks */
 190 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 191 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 192
 193 /* Flash banks JFFS2 should use */
 194 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 195                                         CONFIG_SYS_MAX_NAND_DEVICE)
 196 #define CONFIG_SYS_JFFS2_MEM_NAND
 197 /* use flash_info[2] */
 198 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 199 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 200
 201 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 202 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 203 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 204 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 205                                          CONFIG_SYS_INIT_RAM_SIZE - \
 206                                          GENERATED_GBL_DATA_SIZE)
 207
 208 /* Defines for SPL */
 209 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 210                                          CONFIG_SPL_TEXT_BASE)
 211
 212 #define CONFIG_SPL_BSS_START_ADDR       0x80000000
 213 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 214
 215 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 216 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 217
 218 #define CONFIG_SPL_NAND_BASE
 219 #define CONFIG_SPL_NAND_DRIVERS
 220 #define CONFIG_SPL_NAND_ECC
 221
 222 /* NAND boot config */
 223 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 224 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 225 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 226 #define CONFIG_SYS_NAND_OOBSIZE         64
 227 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 228 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 229 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 230                                                 10, 11, 12, 13}
 231 #define CONFIG_SYS_NAND_ECCSIZE         512
 232 #define CONFIG_SYS_NAND_ECCBYTES        3
 233 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 234 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 235 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 236
 237 /*
 238  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 239  * 64 bytes before this address should be set aside for u-boot.img's
 240  * header. That is 0x800FFFC0--0x80100000 should not be used for any
 241  * other needs.
 242  */
 243 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 244 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 245
 246 #endif /* __CONFIG_H */