2 * am3517_crane.h - Default configuration for AM3517 CraneBoard.
4 * Author: Srinath.R <srinath@mistralsolutions.com>
6 * Based on include/configs/am3517evm.h
8 * Copyright (C) 2011 Mistral Solutions pvt Ltd
10 * SPDX-License-Identifier: GPL-2.0+
17 * High Level Configuration Options
19 #define CONFIG_OMAP 1 /* in a TI OMAP core */
20 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
21 /* Common ARM Erratas */
22 #define CONFIG_ARM_ERRATA_454179
23 #define CONFIG_ARM_ERRATA_430973
24 #define CONFIG_ARM_ERRATA_621766
26 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
28 #include <asm/arch/cpu.h> /* get chip and board defs */
29 #include <asm/arch/omap.h>
32 #define V_OSCK 26000000 /* Clock output from T2 */
33 #define V_SCLK (V_OSCK >> 1)
35 #define CONFIG_MISC_INIT_R
37 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
38 #define CONFIG_SETUP_MEMORY_TAGS 1
39 #define CONFIG_INITRD_TAG 1
40 #define CONFIG_REVISION_TAG 1
43 * Size of malloc() pool
45 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
46 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
51 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
58 * NS16550 Configuration
60 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
62 #define CONFIG_SYS_NS16550_SERIAL
63 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
64 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
67 * select serial console configuration
69 #define CONFIG_CONS_INDEX 3
70 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
71 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
73 /* allow to overwrite serial and ethaddr */
74 #define CONFIG_ENV_OVERWRITE
75 #define CONFIG_BAUDRATE 115200
76 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
78 #define CONFIG_GENERIC_MMC 1
80 #define CONFIG_OMAP_HSMMC 1
81 #define CONFIG_DOS_PARTITION 1
85 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
86 * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
88 #define CONFIG_USB_AM35X 1
89 #define CONFIG_USB_MUSB_HCD 1
91 #ifdef CONFIG_USB_AM35X
93 #ifdef CONFIG_USB_MUSB_HCD
95 #define CONGIG_CMD_STORAGE
97 #ifdef CONFIG_USB_KEYBOARD
98 #define CONFIG_SYS_USB_EVENT_POLL
99 #define CONFIG_PREBOOT "usb start"
100 #endif /* CONFIG_USB_KEYBOARD */
102 #endif /* CONFIG_USB_MUSB_HCD */
104 #ifdef CONFIG_USB_MUSB_UDC
105 /* USB device configuration */
106 #define CONFIG_USB_DEVICE 1
107 #define CONFIG_USB_TTY 1
108 /* Change these to suit your needs */
109 #define CONFIG_USBD_VENDORID 0x0451
110 #define CONFIG_USBD_PRODUCTID 0x5678
111 #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
112 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
113 #endif /* CONFIG_USB_MUSB_UDC */
115 #endif /* CONFIG_USB_AM35X */
117 /* commands to include */
118 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
120 #define CONFIG_CMD_NAND /* NAND support */
122 #define CONFIG_SYS_NO_FLASH
123 #define CONFIG_SYS_I2C
124 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
125 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
126 #define CONFIG_SYS_I2C_OMAP34XX
131 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
133 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
137 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
140 #define CONFIG_JFFS2_NAND
141 /* nand device jffs2 lives on */
142 #define CONFIG_JFFS2_DEV "nand0"
143 /* start of jffs2 partition */
144 #define CONFIG_JFFS2_PART_OFFSET 0x680000
145 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
147 /* Environment information */
149 #define CONFIG_BOOTFILE "uImage"
151 #define CONFIG_EXTRA_ENV_SETTINGS \
152 "loadaddr=0x82000000\0" \
153 "console=ttyS2,115200n8\0" \
155 "mmcargs=setenv bootargs console=${console} " \
156 "root=/dev/mmcblk0p2 rw " \
157 "rootfstype=ext3 rootwait\0" \
158 "nandargs=setenv bootargs console=${console} " \
159 "root=/dev/mtdblock4 rw " \
160 "rootfstype=jffs2\0" \
161 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
162 "bootscript=echo Running bootscript from mmc ...; " \
163 "source ${loadaddr}\0" \
164 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
165 "mmcboot=echo Booting from mmc ...; " \
167 "bootm ${loadaddr}\0" \
168 "nandboot=echo Booting from nand ...; " \
170 "nand read ${loadaddr} 280000 400000; " \
171 "bootm ${loadaddr}\0" \
173 #define CONFIG_BOOTCOMMAND \
174 "mmc dev ${mmcdev}; if mmc rescan; then " \
175 "if run loadbootscript; then " \
178 "if run loaduimage; then " \
180 "else run nandboot; " \
183 "else run nandboot; fi"
185 #define CONFIG_AUTO_COMPLETE 1
187 * Miscellaneous configurable options
189 #define CONFIG_SYS_LONGHELP /* undef to save memory */
190 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
191 /* Print Buffer Size */
192 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
193 sizeof(CONFIG_SYS_PROMPT) + 16)
194 #define CONFIG_SYS_MAXARGS 32 /* max number of command */
196 /* Boot Argument Buffer Size */
197 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
198 /* memtest works on */
199 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
200 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
201 0x01F00000) /* 31MB */
203 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
207 * AM3517 has 12 GP timers, they can be driven by the system clock
208 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
209 * This rate is divided by a local divisor.
211 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
212 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
214 /*-----------------------------------------------------------------------
215 * Physical Memory Map
217 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
218 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
219 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
221 /*-----------------------------------------------------------------------
222 * FLASH and environment organization
225 /* **** PISMO SUPPORT *** */
226 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
228 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
229 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
231 #define CONFIG_SYS_FLASH_BASE NAND_BASE
233 /* Monitor at start of flash */
234 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
236 #define CONFIG_NAND_OMAP_GPMC
237 #define CONFIG_ENV_IS_IN_NAND 1
238 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
240 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
241 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
242 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
244 /*-----------------------------------------------------------------------
245 * CFI FLASH driver setup
247 /* timeout values are in ticks */
248 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
249 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
251 /* Flash banks JFFS2 should use */
252 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
253 CONFIG_SYS_MAX_NAND_DEVICE)
254 #define CONFIG_SYS_JFFS2_MEM_NAND
255 /* use flash_info[2] */
256 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
257 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
259 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
260 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
261 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
262 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
263 CONFIG_SYS_INIT_RAM_SIZE - \
264 GENERATED_GBL_DATA_SIZE)
266 /* Defines for SPL */
267 #define CONFIG_SPL_FRAMEWORK
268 #define CONFIG_SPL_BOARD_INIT
269 #define CONFIG_SPL_NAND_SIMPLE
270 #define CONFIG_SPL_TEXT_BASE 0x40200800
271 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
272 CONFIG_SPL_TEXT_BASE)
274 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
275 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
277 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
278 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
280 #define CONFIG_SPL_NAND_BASE
281 #define CONFIG_SPL_NAND_DRIVERS
282 #define CONFIG_SPL_NAND_ECC
283 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
285 /* NAND boot config */
286 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
287 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
288 #define CONFIG_SYS_NAND_PAGE_COUNT 64
289 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
290 #define CONFIG_SYS_NAND_OOBSIZE 64
291 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
292 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
293 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
295 #define CONFIG_SYS_NAND_ECCSIZE 512
296 #define CONFIG_SYS_NAND_ECCBYTES 3
297 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
298 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
299 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
302 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
303 * 64 bytes before this address should be set aside for u-boot.img's
304 * header. That is 0x800FFFC0--0x80100000 should not be used for any
307 #define CONFIG_SYS_TEXT_BASE 0x80100000
308 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
309 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
311 #endif /* __CONFIG_H */