* Patches by Robert Whaley, 29 Nov 2004:
[platform/kernel/u-boot.git] / include / configs / adsvix.h
1 /*
2  * (C) Copyright 2004
3  * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
4  *
5  * (C) Copyright 2002
6  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
7  *
8  * (C) Copyright 2002
9  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10  * Marius Groeger <mgroeger@sysgo.de>
11  *
12  * Configuation settings for the LUBBOCK board.
13  *
14  * See file CREDITS for list of people who contributed to this
15  * project.
16  *
17  * This program is free software; you can redistribute it and/or
18  * modify it under the terms of the GNU General Public License as
19  * published by the Free Software Foundation; either version 2 of
20  * the License, or (at your option) any later version.
21  *
22  * This program is distributed in the hope that it will be useful,
23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25  * GNU General Public License for more details.
26  *
27  * You should have received a copy of the GNU General Public License
28  * along with this program; if not, write to the Free Software
29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30  * MA 02111-1307 USA
31  */
32
33 #ifndef __CONFIG_H
34 #define __CONFIG_H
35
36 /*
37  * If we are developing, we might want to start armboot from ram
38  * so we MUST NOT initialize critical regs like mem-timing ...
39  */
40 #define CONFIG_INIT_CRITICAL            /* undef for developing */
41 #define RTC
42
43 /*
44  * High Level Configuration Options
45  * (easy to change)
46  */
47 #define CONFIG_PXA27X           1       /* This is an PXA27x CPU    */
48 #define CONFIG_ADSVIX           1       /* on a Adsvix Board     */
49 #define CONFIG_MMC              1
50 #define BOARD_LATE_INIT         1
51
52 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
53
54 /*
55  * Size of malloc() pool
56  */
57 #define CFG_MALLOC_LEN      (CFG_ENV_SIZE + 128*1024)
58 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
59
60 /*
61  * Hardware drivers
62  */
63
64 /*
65  * select serial console configuration
66  */
67 #define CONFIG_FFUART          1       /* we use FFUART on ADSVIX */
68
69 /* allow to overwrite serial and ethaddr */
70 #define CONFIG_ENV_OVERWRITE
71
72 #define CONFIG_BAUDRATE        38400
73
74 #define CONFIG_DOS_PARTITION   1
75
76 #define CONFIG_COMMANDS         ((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA)
77
78 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
79 #include <cmd_confdefs.h>
80
81 #undef CONFIG_SHOW_BOOT_PROGRESS
82
83 #define CONFIG_BOOTDELAY        3
84 #define CONFIG_SERVERIP         192.168.1.99
85 #define CONFIG_BOOTCOMMAND      "run boot_flash"
86 #define CONFIG_BOOTARGS         "console=ttyS0,38400 ramdisk_size=12288"\
87                                 " rw root=/dev/ram initrd=0xa0800000,5m"
88
89 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
90         "program_boot_cf="                                              \
91                         "mw.b 0xa0010000 0xff 0x20000; "                \
92                         "if      pinit on && "                          \
93                                 "ide reset && "                         \
94                                 "fatload ide 0 0xa0010000 u-boot.bin; " \
95                         "then "                                         \
96                                 "protect off 0x0 0x1ffff; "             \
97                                 "erase 0x0 0x1ffff; "                   \
98                                 "cp.b 0xa0010000 0x0 0x20000; "         \
99                         "fi\0"                                          \
100         "program_uzImage_cf="                                           \
101                         "mw.b 0xa0010000 0xff 0x180000; "               \
102                         "if      pinit on && "                          \
103                                 "ide reset && "                         \
104                                 "fatload ide 0 0xa0010000 uzImage; "    \
105                         "then "                                         \
106                                 "protect off 0x40000 0x1bffff; "        \
107                                 "erase 0x40000 0x1bffff; "              \
108                                 "cp.b 0xa0010000 0x40000 0x180000; "    \
109                         "fi\0"                                          \
110         "program_ramdisk_cf="                                           \
111                         "mw.b 0xa0010000 0xff 0x500000; "               \
112                         "if      pinit on && "                          \
113                                 "ide reset && "                         \
114                                 "fatload ide 0 0xa0010000 ramdisk.gz; " \
115                         "then "                                         \
116                                 "protect off 0x1c0000 0x6bffff; "       \
117                                 "erase 0x1c0000 0x6bffff; "             \
118                                 "cp.b 0xa0010000 0x1c0000 0x500000; "   \
119                         "fi\0"                                          \
120         "boot_cf="                                                      \
121                         "if      pinit on && "                          \
122                                 "ide reset && "                         \
123                                 "fatload ide 0 0xa0030000 uzImage && "  \
124                                 "fatload ide 0 0xa0800000 ramdisk.gz; " \
125                         "then "                                         \
126                                 "bootm 0xa0030000; "                    \
127                         "fi\0"                                          \
128         "program_boot_mmc="                                             \
129                         "mw.b 0xa0010000 0xff 0x20000; "                \
130                         "if      mmcinit && "                           \
131                                 "fatload mmc 0 0xa0010000 u-boot.bin; " \
132                         "then "                                         \
133                                 "protect off 0x0 0x1ffff; "             \
134                                 "erase 0x0 0x1ffff; "                   \
135                                 "cp.b 0xa0010000 0x0 0x20000; "         \
136                         "fi\0"                                          \
137         "program_uzImage_mmc="                                          \
138                         "mw.b 0xa0010000 0xff 0x180000; "               \
139                         "if      mmcinit && "                           \
140                                 "fatload mmc 0 0xa0010000 uzImage; "    \
141                         "then "                                         \
142                                 "protect off 0x40000 0x1bffff; "        \
143                                 "erase 0x40000 0x1bffff; "              \
144                                 "cp.b 0xa0010000 0x40000 0x180000; "    \
145                         "fi\0"                                          \
146         "program_ramdisk_mmc="                                          \
147                         "mw.b 0xa0010000 0xff 0x500000; "               \
148                         "if      mmcinit && "                           \
149                                 "fatload mmc 0 0xa0010000 ramdisk.gz; " \
150                         "then "                                         \
151                                 "protect off 0x1c0000 0x6bffff; "       \
152                                 "erase 0x1c0000 0x6bffff; "             \
153                                 "cp.b 0xa0010000 0x1c0000 0x500000; "   \
154                         "fi\0"                                          \
155         "boot_mmc="                                                     \
156                         "if      mmcinit && "                           \
157                                 "fatload mmc 0 0xa0030000 uzImage && "  \
158                                 "fatload mmc 0 0xa0800000 ramdisk.gz; " \
159                         "then "                                         \
160                                 "bootm 0xa0030000; "                    \
161                         "fi\0"                                          \
162         "boot_flash="                                                   \
163                         "cp.b 0x1c0000 0xa0800000 0x500000; "           \
164                         "bootm 0x40000\0"                               \
165
166 #define CONFIG_SETUP_MEMORY_TAGS 1
167 #define CONFIG_CMDLINE_TAG       1      /* enable passing of ATAGs      */
168 /* #define CONFIG_INITRD_TAG     1 */
169
170 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
171 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
172 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
173 #endif
174
175 /*
176  * Miscellaneous configurable options
177  */
178 #define CFG_HUSH_PARSER         1
179 #define CFG_PROMPT_HUSH_PS2     "> "
180
181 #define CFG_LONGHELP                            /* undef to save memory         */
182 #ifdef CFG_HUSH_PARSER
183 #define CFG_PROMPT              "$ "            /* Monitor Command Prompt */
184 #else
185 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt */
186 #endif
187 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
188 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
189 #define CFG_MAXARGS             16              /* max number of command args   */
190 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
191 #define CFG_DEVICE_NULLDEV      1
192
193 #define CFG_MEMTEST_START       0xa0400000      /* memtest works on     */
194 #define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
195
196 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
197
198 #define CFG_LOAD_ADDR           0xa1000000      /* default load address */
199
200 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
201 #define CFG_CPUSPEED            0x207           /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
202
203                                                 /* valid baudrates */
204 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
205
206 #define CFG_MMC_BASE            0xF0000000
207
208 /*
209  * Stack sizes
210  *
211  * The stack sizes are set up in start.S using the settings below
212  */
213 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
214 #ifdef CONFIG_USE_IRQ
215 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
216 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
217 #endif
218
219 /*
220  * Physical Memory Map
221  */
222 #define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
223 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
224 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
225 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
226 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
227 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
228 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
229 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
230 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
231
232 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
233
234 #define CFG_DRAM_BASE           0xa0000000
235 #define CFG_DRAM_SIZE           0x04000000
236
237 #define CFG_FLASH_BASE          PHYS_FLASH_1
238
239 /*
240  * GPIO settings
241  */
242
243 #define CFG_GPSR0_VAL           0x00018004
244 #define CFG_GPSR1_VAL           0x004F0080
245 #define CFG_GPSR2_VAL           0x13EFC000
246 #define CFG_GPSR3_VAL           0x0006E032
247 #define CFG_GPCR0_VAL           0x084AFE1A
248 #define CFG_GPCR1_VAL           0x003003F2
249 #define CFG_GPCR2_VAL           0x0C014000
250 #define CFG_GPCR3_VAL           0x00000C00
251 #define CFG_GPDR0_VAL           0xCBC3BFFC
252 #define CFG_GPDR1_VAL           0x00FFABF3
253 #define CFG_GPDR2_VAL           0x1EEFFC00
254 #define CFG_GPDR3_VAL           0x0187EC32
255 #define CFG_GAFR0_L_VAL         0x84400000
256 #define CFG_GAFR0_U_VAL         0xA51A8010
257 #define CFG_GAFR1_L_VAL         0x699A955A
258 #define CFG_GAFR1_U_VAL         0x0005A0AA
259 #define CFG_GAFR2_L_VAL         0x40000000
260 #define CFG_GAFR2_U_VAL         0x0109A400
261 #define CFG_GAFR3_L_VAL         0x54000000
262 #define CFG_GAFR3_U_VAL         0x00001409
263
264 #define CFG_PSSR_VAL            0x20
265
266 /*
267  * Clock settings
268  */
269 #define CFG_CKEN                0x00400200
270 #define CFG_CCCR                0x02000290 /*   520Mhz */
271 /* #define CFG_CCCR             0x02000210  416 Mhz */
272
273 /*
274  * Memory settings
275  */
276
277 #define CFG_MSC0_VAL            0x23F2B3DB
278 #define CFG_MSC1_VAL            0x0000CCD1
279 #define CFG_MSC2_VAL            0x0000B884
280 #define CFG_MDCNFG_VAL          0x08000AC8
281 #define CFG_MDREFR_VAL          0x0000001E
282 #define CFG_MDMRS_VAL           0x00000000
283
284 #define CFG_FLYCNFG_VAL         0x00010001
285 #define CFG_SXCNFG_VAL          0x40044004
286
287 /*
288  * PCMCIA and CF Interfaces
289  */
290 #define CFG_MECR_VAL            0x00000002
291 #define CFG_MCMEM0_VAL          0x00004204
292 #define CFG_MCMEM1_VAL          0x00000000
293 #define CFG_MCATT0_VAL          0x00010504
294 #define CFG_MCATT1_VAL          0x00000000
295 #define CFG_MCIO0_VAL           0x00008407
296 #define CFG_MCIO1_VAL           0x00000000
297
298 #define CONFIG_PXA_PCMCIA 1
299 #define CONFIG_PXA_IDE 1
300
301 #define CONFIG_PCMCIA_SLOT_A 1
302 /* just to keep build system happy  */
303
304 #define CFG_PCMCIA_MEM_ADDR     0x28000000
305 #define CFG_PCMCIA_MEM_SIZE     0x04000000
306
307
308 #define CFG_IDE_MAXBUS          1
309 /* max. 1 IDE bus               */
310 #define CFG_IDE_MAXDEVICE       1
311 /* max. 1 drive per IDE bus     */
312
313 #define CFG_ATA_IDE0_OFFSET     0x0000
314
315 #define CFG_ATA_BASE_ADDR       0x20000000
316
317 /* Offset for data I/O                  */
318 #define CFG_ATA_DATA_OFFSET     0x1f0
319
320 /* Offset for normal register accesses  */
321 #define CFG_ATA_REG_OFFSET      0x1f0
322
323 /* Offset for alternate registers       */
324 #define CFG_ATA_ALT_OFFSET      0x3f0
325
326 /*
327  * FLASH and environment organization
328  */
329
330 #define CFG_FLASH_CFI
331 #define CFG_FLASH_CFI_DRIVER    1
332
333 #define CFG_MONITOR_BASE        0
334 #define CFG_MONITOR_LEN         0x20000
335
336 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
337 #define CFG_MAX_FLASH_SECT      4 + 255  /* max number of sectors on one chip    */
338
339 /* timeout values are in ticks */
340 #define CFG_FLASH_ERASE_TOUT    (25*CFG_HZ) /* Timeout for Flash Erase */
341 #define CFG_FLASH_WRITE_TOUT    (25*CFG_HZ) /* Timeout for Flash Write */
342
343 /* write flash less slowly */
344 #define CFG_FLASH_USE_BUFFER_WRITE 1
345
346 /* Flash environment locations */
347 #define CFG_ENV_IS_IN_FLASH     1
348 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + CFG_MONITOR_LEN)        /* Addr of Environment Sector   */
349 #define CFG_ENV_SIZE            0x20000 /* Total Size of Environment            */
350 #define CFG_ENV_SECT_SIZE       0x20000 /* Total Size of Environment Sector     */
351
352 #endif  /* __CONFIG_H */