include/configs/adsvix.h

   1 /*
   2  * (C) Copyright 2004
   3  * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
   4  *
   5  * (C) Copyright 2002
   6  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   7  *
   8  * (C) Copyright 2002
   9  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  10  * Marius Groeger <mgroeger@sysgo.de>
  11  *
  12  * Configuation settings for the LUBBOCK board.
  13  *
  14  * See file CREDITS for list of people who contributed to this
  15  * project.
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30  * MA 02111-1307 USA
  31  */
  32
  33 #ifndef __CONFIG_H
  34 #define __CONFIG_H
  35
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40 #define CONFIG_PXA27X           1       /* This is an PXA27x CPU    */
  41 #define CONFIG_ADSVIX           1       /* on a Adsvix Board     */
  42 #define CONFIG_MMC              1
  43 #define BOARD_LATE_INIT         1
  44
  45 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  46
  47 #define RTC
  48
  49 /*
  50  * Size of malloc() pool
  51  */
  52 #define CFG_MALLOC_LEN      (CFG_ENV_SIZE + 128*1024)
  53 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  54
  55 /*
  56  * Hardware drivers
  57  */
  58
  59 /*
  60  * select serial console configuration
  61  */
  62 #define CONFIG_FFUART          1       /* we use FFUART on ADSVIX */
  63
  64 /* allow to overwrite serial and ethaddr */
  65 #define CONFIG_ENV_OVERWRITE
  66
  67 #define CONFIG_BAUDRATE        38400
  68
  69 #define CONFIG_DOS_PARTITION   1
  70
  71
  72 /*
  73  * Command line configuration.
  74  */
  75 #include <config_cmd_default.h>
  76
  77 #define CONFIG_CMD_FAT
  78 #define CONFIG_CMD_IDE
  79 #define CONFIG_CMD_MMC
  80 #define CONFIG_CMD_PCMCIA
  81
  82 #undef CONFIG_CMD_NET
  83
  84
  85 #undef CONFIG_SHOW_BOOT_PROGRESS
  86
  87 #define CONFIG_BOOTDELAY        3
  88 #define CONFIG_SERVERIP         192.168.1.99
  89 #define CONFIG_BOOTCOMMAND      "run boot_flash"
  90 #define CONFIG_BOOTARGS         "console=ttyS0,38400 ramdisk_size=12288"\
  91                                 " rw root=/dev/ram initrd=0xa0800000,5m"
  92
  93 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  94         "program_boot_cf="                                              \
  95                         "mw.b 0xa0010000 0xff 0x20000; "                \
  96                         "if      pinit on && "                          \
  97                                 "ide reset && "                         \
  98                                 "fatload ide 0 0xa0010000 u-boot.bin; " \
  99                         "then "                                         \
 100                                 "protect off 0x0 0x1ffff; "             \
 101                                 "erase 0x0 0x1ffff; "                   \
 102                                 "cp.b 0xa0010000 0x0 0x20000; "         \
 103                         "fi\0"                                          \
 104         "program_uzImage_cf="                                           \
 105                         "mw.b 0xa0010000 0xff 0x180000; "               \
 106                         "if      pinit on && "                          \
 107                                 "ide reset && "                         \
 108                                 "fatload ide 0 0xa0010000 uzImage; "    \
 109                         "then "                                         \
 110                                 "protect off 0x40000 0x1bffff; "        \
 111                                 "erase 0x40000 0x1bffff; "              \
 112                                 "cp.b 0xa0010000 0x40000 0x180000; "    \
 113                         "fi\0"                                          \
 114         "program_ramdisk_cf="                                           \
 115                         "mw.b 0xa0010000 0xff 0x500000; "               \
 116                         "if      pinit on && "                          \
 117                                 "ide reset && "                         \
 118                                 "fatload ide 0 0xa0010000 ramdisk.gz; " \
 119                         "then "                                         \
 120                                 "protect off 0x1c0000 0x6bffff; "       \
 121                                 "erase 0x1c0000 0x6bffff; "             \
 122                                 "cp.b 0xa0010000 0x1c0000 0x500000; "   \
 123                         "fi\0"                                          \
 124         "boot_cf="                                                      \
 125                         "if      pinit on && "                          \
 126                                 "ide reset && "                         \
 127                                 "fatload ide 0 0xa0030000 uzImage && "  \
 128                                 "fatload ide 0 0xa0800000 ramdisk.gz; " \
 129                         "then "                                         \
 130                                 "bootm 0xa0030000; "                    \
 131                         "fi\0"                                          \
 132         "program_boot_mmc="                                             \
 133                         "mw.b 0xa0010000 0xff 0x20000; "                \
 134                         "if      mmcinit && "                           \
 135                                 "fatload mmc 0 0xa0010000 u-boot.bin; " \
 136                         "then "                                         \
 137                                 "protect off 0x0 0x1ffff; "             \
 138                                 "erase 0x0 0x1ffff; "                   \
 139                                 "cp.b 0xa0010000 0x0 0x20000; "         \
 140                         "fi\0"                                          \
 141         "program_uzImage_mmc="                                          \
 142                         "mw.b 0xa0010000 0xff 0x180000; "               \
 143                         "if      mmcinit && "                           \
 144                                 "fatload mmc 0 0xa0010000 uzImage; "    \
 145                         "then "                                         \
 146                                 "protect off 0x40000 0x1bffff; "        \
 147                                 "erase 0x40000 0x1bffff; "              \
 148                                 "cp.b 0xa0010000 0x40000 0x180000; "    \
 149                         "fi\0"                                          \
 150         "program_ramdisk_mmc="                                          \
 151                         "mw.b 0xa0010000 0xff 0x500000; "               \
 152                         "if      mmcinit && "                           \
 153                                 "fatload mmc 0 0xa0010000 ramdisk.gz; " \
 154                         "then "                                         \
 155                                 "protect off 0x1c0000 0x6bffff; "       \
 156                                 "erase 0x1c0000 0x6bffff; "             \
 157                                 "cp.b 0xa0010000 0x1c0000 0x500000; "   \
 158                         "fi\0"                                          \
 159         "boot_mmc="                                                     \
 160                         "if      mmcinit && "                           \
 161                                 "fatload mmc 0 0xa0030000 uzImage && "  \
 162                                 "fatload mmc 0 0xa0800000 ramdisk.gz; " \
 163                         "then "                                         \
 164                                 "bootm 0xa0030000; "                    \
 165                         "fi\0"                                          \
 166         "boot_flash="                                                   \
 167                         "cp.b 0x1c0000 0xa0800000 0x500000; "           \
 168                         "bootm 0x40000\0"                               \
 169
 170 #define CONFIG_SETUP_MEMORY_TAGS 1
 171 #define CONFIG_CMDLINE_TAG       1      /* enable passing of ATAGs      */
 172 /* #define CONFIG_INITRD_TAG     1 */
 173
 174 #if defined(CONFIG_CMD_KGDB)
 175 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 176 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 177 #endif
 178
 179 /*
 180  * Miscellaneous configurable options
 181  */
 182 #define CFG_HUSH_PARSER         1
 183 #define CFG_PROMPT_HUSH_PS2     "> "
 184
 185 #define CFG_LONGHELP                            /* undef to save memory         */
 186 #ifdef CFG_HUSH_PARSER
 187 #define CFG_PROMPT              "$ "            /* Monitor Command Prompt */
 188 #else
 189 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt */
 190 #endif
 191 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 192 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 193 #define CFG_MAXARGS             16              /* max number of command args   */
 194 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 195 #define CFG_DEVICE_NULLDEV      1
 196
 197 #define CFG_MEMTEST_START       0xa0400000      /* memtest works on     */
 198 #define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 199
 200 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 201
 202 #define CFG_LOAD_ADDR           0xa1000000      /* default load address */
 203
 204 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 205 #define CFG_CPUSPEED            0x207           /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
 206
 207                                                 /* valid baudrates */
 208 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 209
 210 #define CFG_MMC_BASE            0xF0000000
 211
 212 /*
 213  * Stack sizes
 214  *
 215  * The stack sizes are set up in start.S using the settings below
 216  */
 217 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 218 #ifdef CONFIG_USE_IRQ
 219 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 220 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 221 #endif
 222
 223 /*
 224  * Physical Memory Map
 225  */
 226 #define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
 227 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 228 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 229 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 230 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 231 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 232 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 233 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 234 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 235
 236 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 237
 238 #define CFG_DRAM_BASE           0xa0000000
 239 #define CFG_DRAM_SIZE           0x04000000
 240
 241 #define CFG_FLASH_BASE          PHYS_FLASH_1
 242
 243 /*
 244  * GPIO settings
 245  */
 246
 247 #define CFG_GPSR0_VAL           0x00018004
 248 #define CFG_GPSR1_VAL           0x004F0080
 249 #define CFG_GPSR2_VAL           0x13EFC000
 250 #define CFG_GPSR3_VAL           0x0006E032
 251 #define CFG_GPCR0_VAL           0x084AFE1A
 252 #define CFG_GPCR1_VAL           0x003003F2
 253 #define CFG_GPCR2_VAL           0x0C014000
 254 #define CFG_GPCR3_VAL           0x00000C00
 255 #define CFG_GPDR0_VAL           0xCBC3BFFC
 256 #define CFG_GPDR1_VAL           0x00FFABF3
 257 #define CFG_GPDR2_VAL           0x1EEFFC00
 258 #define CFG_GPDR3_VAL           0x0187EC32
 259 #define CFG_GAFR0_L_VAL         0x84400000
 260 #define CFG_GAFR0_U_VAL         0xA51A8010
 261 #define CFG_GAFR1_L_VAL         0x699A955A
 262 #define CFG_GAFR1_U_VAL         0x0005A0AA
 263 #define CFG_GAFR2_L_VAL         0x40000000
 264 #define CFG_GAFR2_U_VAL         0x0109A400
 265 #define CFG_GAFR3_L_VAL         0x54000000
 266 #define CFG_GAFR3_U_VAL         0x00001409
 267
 268 #define CFG_PSSR_VAL            0x20
 269
 270 /*
 271  * Clock settings
 272  */
 273 #define CFG_CKEN                0x00400200
 274 #define CFG_CCCR                0x02000290 /*   520Mhz */
 275 /* #define CFG_CCCR             0x02000210  416 Mhz */
 276
 277 /*
 278  * Memory settings
 279  */
 280
 281 #define CFG_MSC0_VAL            0x23F2B3DB
 282 #define CFG_MSC1_VAL            0x0000CCD1
 283 #define CFG_MSC2_VAL            0x0000B884
 284 #define CFG_MDCNFG_VAL          0x08000AC8
 285 #define CFG_MDREFR_VAL          0x0000001E
 286 #define CFG_MDMRS_VAL           0x00000000
 287
 288 #define CFG_FLYCNFG_VAL         0x00010001
 289 #define CFG_SXCNFG_VAL          0x40044004
 290
 291 /*
 292  * PCMCIA and CF Interfaces
 293  */
 294 #define CFG_MECR_VAL            0x00000002
 295 #define CFG_MCMEM0_VAL          0x00004204
 296 #define CFG_MCMEM1_VAL          0x00000000
 297 #define CFG_MCATT0_VAL          0x00010504
 298 #define CFG_MCATT1_VAL          0x00000000
 299 #define CFG_MCIO0_VAL           0x00008407
 300 #define CFG_MCIO1_VAL           0x00000000
 301
 302 #define CONFIG_PXA_PCMCIA 1
 303 #define CONFIG_PXA_IDE 1
 304
 305 #define CONFIG_PCMCIA_SLOT_A 1
 306 /* just to keep build system happy  */
 307
 308 #define CFG_PCMCIA_MEM_ADDR     0x28000000
 309 #define CFG_PCMCIA_MEM_SIZE     0x04000000
 310
 311
 312 #define CFG_IDE_MAXBUS          1
 313 /* max. 1 IDE bus               */
 314 #define CFG_IDE_MAXDEVICE       1
 315 /* max. 1 drive per IDE bus     */
 316
 317 #define CFG_ATA_IDE0_OFFSET     0x0000
 318
 319 #define CFG_ATA_BASE_ADDR       0x20000000
 320
 321 /* Offset for data I/O                  */
 322 #define CFG_ATA_DATA_OFFSET     0x1f0
 323
 324 /* Offset for normal register accesses  */
 325 #define CFG_ATA_REG_OFFSET      0x1f0
 326
 327 /* Offset for alternate registers       */
 328 #define CFG_ATA_ALT_OFFSET      0x3f0
 329
 330 /*
 331  * FLASH and environment organization
 332  */
 333
 334 #define CFG_FLASH_CFI
 335 #define CFG_FLASH_CFI_DRIVER    1
 336
 337 #define CFG_MONITOR_BASE        0
 338 #define CFG_MONITOR_LEN         0x20000
 339
 340 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 341 #define CFG_MAX_FLASH_SECT      4 + 255  /* max number of sectors on one chip    */
 342
 343 /* timeout values are in ticks */
 344 #define CFG_FLASH_ERASE_TOUT    (25*CFG_HZ) /* Timeout for Flash Erase */
 345 #define CFG_FLASH_WRITE_TOUT    (25*CFG_HZ) /* Timeout for Flash Write */
 346
 347 /* write flash less slowly */
 348 #define CFG_FLASH_USE_BUFFER_WRITE 1
 349
 350 /* Flash environment locations */
 351 #define CFG_ENV_IS_IN_FLASH     1
 352 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + CFG_MONITOR_LEN)        /* Addr of Environment Sector   */
 353 #define CFG_ENV_SIZE            0x20000 /* Total Size of Environment            */
 354 #define CFG_ENV_SECT_SIZE       0x20000 /* Total Size of Environment Sector     */
 355
 356 #endif  /* __CONFIG_H */