2 * (C) Copyright 2007 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * ADS5121 board configuration file
34 * Memory map for the ADS5121 board:
36 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
37 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
38 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
39 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
40 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
44 * High Level Configuration Options
46 #define CONFIG_E300 1 /* E300 Family */
47 #define CONFIG_MPC512X 1 /* MPC512X family */
51 #define CFG_MPC512X_CLKIN 66000000 /* in Hz */
53 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
55 #define CFG_IMMR 0x80000000
57 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
58 #define CFG_MEMTEST_END 0x00400000
61 * DDR Setup - manually set all parameters as there's no SPD etc.
63 #define CFG_DDR_SIZE 256 /* MB */
64 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
65 #define CFG_SDRAM_BASE CFG_DDR_BASE
67 /* DDR Controller Configuration
70 [31:31] MDDRC Soft Reset: Diabled
71 [30:30] DRAM CKE pin: Enabled
72 [29:29] DRAM CLK: Enabled
73 [28:28] Command Mode: Enabled (For initialization only)
74 [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
75 [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
76 [20:19] Read Test: DON'T USE
77 [18:18] Self Refresh: Enabled
78 [17:17] 16bit Mode: Disabled
79 [16:13] Ready Delay: 2
80 [12:12] Half DQS Delay: Disabled
81 [11:11] Quarter DQS Delay: Disabled
82 [10:08] Write Delay: 2
83 [07:07] Early ODT: Disabled
84 [06:06] On DIE Termination: Disabled
85 [05:05] FIFO Overflow Clear: DON'T USE here
86 [04:04] FIFO Underflow Clear: DON'T USE here
87 [03:03] FIFO Overflow Pending: DON'T USE here
88 [02:02] FIFO Underlfow Pending: DON'T USE here
89 [01:01] FIFO Overlfow Enabled: Enabled
90 [00:00] FIFO Underflow Enabled: Enabled
92 [31:16] DRAM Refresh Time: 0 CSB clocks
93 [15:8] DRAM Command Time: 0 CSB clocks
94 [07:00] DRAM Precharge Time: 0 CSB clocks
111 #define CFG_MDDRC_SYS_CFG 0xF8604200
112 #define CFG_MDDRC_SYS_CFG_RUN 0xE8604200
113 #define CFG_MDDRC_SYS_CFG_EN 0x30000000
114 #define CFG_MDDRC_TIME_CFG0 0x0000281E
115 #define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E
116 #define CFG_MDDRC_TIME_CFG1 0x54EC1168
117 #define CFG_MDDRC_TIME_CFG2 0x35210864
119 #define CFG_MICRON_NOP 0x01380000
120 #define CFG_MICRON_PCHG_ALL 0x01100400
121 #define CFG_MICRON_MR 0x01000022
122 #define CFG_MICRON_EM2 0x01020000
123 #define CFG_MICRON_EM3 0x01030000
124 #define CFG_MICRON_EN_DLL 0x01010000
125 #define CFG_MICRON_RST_DLL 0x01000932
126 #define CFG_MICRON_RFSH 0x01080000
127 #define CFG_MICRON_INIT_DEV_OP 0x01000832
128 #define CFG_MICRON_OCD_DEFAULT 0x01010780
129 #define CFG_MICRON_OCD_EXIT 0x01010400
131 /* DDR Priority Manager Configuration */
132 #define CFG_MDDRCGRP_PM_CFG1 0x000777AA
133 #define CFG_MDDRCGRP_PM_CFG2 0x00000055
134 #define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000
135 #define CFG_MDDRCGRP_LUT0_MU 0x11111117
136 #define CFG_MDDRCGRP_LUT0_ML 0x7777777A
137 #define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE
138 #define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE
139 #define CFG_MDDRCGRP_LUT2_MU 0x44444444
140 #define CFG_MDDRCGRP_LUT2_ML 0x44444444
141 #define CFG_MDDRCGRP_LUT3_MU 0x55555555
142 #define CFG_MDDRCGRP_LUT3_ML 0x55555558
143 #define CFG_MDDRCGRP_LUT4_MU 0x11111111
144 #define CFG_MDDRCGRP_LUT4_ML 0x1111117C
145 #define CFG_MDDRCGRP_LUT0_AU 0x33333377
146 #define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE
147 #define CFG_MDDRCGRP_LUT1_AU 0x11111111
148 #define CFG_MDDRCGRP_LUT1_AL 0x11111111
149 #define CFG_MDDRCGRP_LUT2_AU 0x11111111
150 #define CFG_MDDRCGRP_LUT2_AL 0x11111111
151 #define CFG_MDDRCGRP_LUT3_AU 0x11111111
152 #define CFG_MDDRCGRP_LUT3_AL 0x11111111
153 #define CFG_MDDRCGRP_LUT4_AU 0x11111111
154 #define CFG_MDDRCGRP_LUT4_AL 0x11111111
157 * NOR FLASH on the Local Bus
159 #define CFG_FLASH_CFI /* use the Common Flash Interface */
160 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
161 #define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */
162 #define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */
163 #define CFG_FLASH_USE_BUFFER_WRITE
165 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
166 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
167 #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
169 #undef CFG_FLASH_CHECKSUM
172 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
175 #define CFG_CPLD_BASE 0x82000000
176 #define CFG_CPLD_SIZE 0x00010000 /* 64 KB */
178 #define CFG_SRAM_BASE 0x30000000
179 #define CFG_SRAM_SIZE 0x00020000 /* 128 KB */
181 #define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
182 #define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
184 /* Use SRAM for initial stack */
185 #define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
186 #define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */
188 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
189 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
190 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
192 #define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
193 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
194 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
199 #define CONFIG_CONS_INDEX 1
200 #undef CONFIG_SERIAL_SOFTWARE_FIFO
203 * Serial console configuration
205 #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
206 #if CONFIG_PSC_CONSOLE != 3
207 #error CONFIG_PSC_CONSOLE must be 3
209 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
210 #define CFG_BAUDRATE_TABLE \
211 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
213 #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
214 #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
215 #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
216 #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
218 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
219 /* Use the HUSH parser */
220 #define CFG_HUSH_PARSER
221 #ifdef CFG_HUSH_PARSER
222 #define CFG_PROMPT_HUSH_PS2 "> "
226 #define CONFIG_HARD_I2C /* I2C with hardware support */
227 #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
228 #define CONFIG_I2C_MULTI_BUS
229 #define CONFIG_I2C_CMD_TREE
230 #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
231 #define CFG_I2C_SLAVE 0x7F
233 #define CFG_I2C_NOPROBES {{0,0x69}} * Don't probe these addrs */
237 * Ethernet configuration
239 #define CONFIG_MPC512x_FEC 1
240 #define CONFIG_NET_MULTI
241 #define CONFIG_PHY_ADDR 0x1
242 #define CONFIG_MII 1 /* MII PHY management */
243 #define CONFIG_ETHADDR 00:e0:5e:00:e5:14
247 * Configure on-board RTC
249 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
250 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
256 #define CFG_ENV_IS_IN_FLASH 1
257 /* This has to be a multiple of the Flash sector size */
258 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
259 #define CFG_ENV_SIZE 0x2000
260 #define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
262 /* Address and size of Redundant Environment Sector */
263 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
264 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
266 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
267 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
269 #if defined(CONFIG_PCI)
270 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
276 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
283 #include <cmd_confdefs.h>
286 * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
287 * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
288 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
289 * to chapter 36 of the MPC5121e Reference Manual.
291 #define CONFIG_WATCHDOG /* enable watchdog */
292 #define CFG_WATCHDOG_VALUE 0xFFFF
295 * Miscellaneous configurable options
297 #define CFG_LONGHELP /* undef to save memory */
298 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
299 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
301 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
302 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
304 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
308 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
309 #define CFG_MAXARGS 16 /* max number of command args */
310 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
311 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
314 * For booting Linux, the board info and command line data
315 * have to be in the first 8 MB of memory, since this is
316 * the maximum mapped by the Linux kernel during initialization.
318 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
320 /* Cache Configuration */
321 #define CFG_DCACHE_SIZE 32768
322 #define CFG_CACHELINE_SIZE 32
323 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
324 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
327 #define CFG_HID0_INIT 0x000000000
328 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
329 #define CFG_HID2 HID2_HBE
332 * Internal Definitions
336 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
337 #define BOOTFLAG_WARM 0x02 /* Software reboot */
339 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
340 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
341 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
345 * Environment Configuration
347 #define CONFIG_ENV_OVERWRITE
349 #define CONFIG_HOSTNAME ads5121
350 #define CONFIG_ROOTPATH /nfsroot/rootfs
351 #define CONFIG_BOOTFILE uImage
353 #define CONFIG_IPADDR 192.168.160.77
354 #define CONFIG_SERVERIP 192.168.1.1
355 #define CONFIG_GATEWAYIP 192.168.1.1
356 #define CONFIG_NETMASK 255.255.0.0
358 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
360 //#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
361 #define CONFIG_BOOTDELAY -1
362 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
364 #define CONFIG_BAUDRATE 115200
366 #define CONFIG_PREBOOT "echo;" \
367 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
370 #define CONFIG_EXTRA_ENV_SETTINGS \
372 "nfsargs=setenv bootargs root=/dev/nfs rw " \
373 "nfsroot=${serverip}:${rootpath}\0" \
374 "ramargs=setenv bootargs root=/dev/ram rw\0" \
375 "addip=setenv bootargs ${bootargs} " \
376 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
377 ":${hostname}:${netdev}:off panic=1\0" \
378 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
379 "flash_nfs=run nfsargs addip addtty;" \
380 "bootm ${kernel_addr}\0" \
381 "flash_self=run ramargs addip addtty;" \
382 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
383 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
385 "load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \
386 "update=protect off fff00000 fff3ffff; " \
387 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
388 "upd=run load;run update\0" \
391 #define CONFIG_NFSBOOTCOMMAND \
392 "setenv bootargs root=/dev/nfs rw " \
393 "nfsroot=$serverip:$rootpath " \
394 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
395 "console=$consoledev,$baudrate $othbootargs;" \
396 "tftp $loadaddr $bootfile;" \
397 "tftp $fdtaddr $fdtfile;" \
398 "bootm $loadaddr - $fdtaddr"
400 #define CONFIG_RAMBOOTCOMMAND \
401 "setenv bootargs root=/dev/ram rw " \
402 "console=$consoledev,$baudrate $othbootargs;" \
403 "tftp $ramdiskaddr $ramdiskfile;" \
404 "tftp $loadaddr $bootfile;" \
405 "tftp $fdtaddr $fdtfile;" \
406 "bootm $loadaddr $ramdiskaddr $fdtaddr"
408 #define CONFIG_BOOTCOMMAND "run flash_self"
410 #endif /* __CONFIG_H */