include/configs/adp-ag101p.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch-ag101/ag101.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_USE_INTERRUPT
  17
  18 #define CONFIG_ARCH_MAP_SYSMEM
  19
  20 #define CONFIG_BOOTP_SERVERIP
  21
  22 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  23 #define CONFIG_MEM_REMAP
  24 #endif
  25
  26 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  27 #ifdef CONFIG_OF_CONTROL
  28 #undef CONFIG_OF_SEPARATE
  29 #define CONFIG_OF_EMBED
  30 #endif
  31 #endif
  32
  33 /*
  34  * Timer
  35  */
  36 #define CONFIG_SYS_CLK_FREQ     39062500
  37 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  38
  39 /*
  40  * Use Externel CLOCK or PCLK
  41  */
  42 #undef CONFIG_FTRTC010_EXTCLK
  43
  44 #ifndef CONFIG_FTRTC010_EXTCLK
  45 #define CONFIG_FTRTC010_PCLK
  46 #endif
  47
  48 #ifdef CONFIG_FTRTC010_EXTCLK
  49 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  50 #else
  51 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  52 #endif
  53
  54 #define TIMER_LOAD_VAL  0xffffffff
  55
  56 /*
  57  * Real Time Clock
  58  */
  59 #define CONFIG_RTC_FTRTC010
  60
  61 /*
  62  * Real Time Clock Divider
  63  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  64  */
  65 #define OSC_5MHZ                        (5*1000000)
  66 #define OSC_CLK                         (4*OSC_5MHZ)
  67 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  68
  69 /*
  70  * Serial console configuration
  71  */
  72
  73 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  74 #define CONFIG_SYS_NS16550_SERIAL
  75 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  76 #ifndef CONFIG_DM_SERIAL
  77 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  78 #endif
  79 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  80
  81 /*
  82  * Miscellaneous configurable options
  83  */
  84
  85 /*
  86  * Size of malloc() pool
  87  */
  88 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  89 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
  90
  91 /*
  92  * AHB Controller configuration
  93  */
  94 #define CONFIG_FTAHBC020S
  95
  96 #ifdef CONFIG_FTAHBC020S
  97 #include <faraday/ftahbc020s.h>
  98
  99 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
 100 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
 101
 102 /*
 103  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
 104  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
 105  * in C language.
 106  */
 107 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
 108         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
 109                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 110 #endif
 111
 112 /*
 113  * Watchdog
 114  */
 115 #define CONFIG_FTWDT010_WATCHDOG
 116
 117 /*
 118  * PMU Power controller configuration
 119  */
 120 #define CONFIG_PMU
 121 #define CONFIG_FTPMU010_POWER
 122
 123 #ifdef CONFIG_FTPMU010_POWER
 124 #include <faraday/ftpmu010.h>
 125 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 126 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 127                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 128                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 129                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 130                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 131                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 132                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 133 #endif
 134
 135 /*
 136  * SDRAM controller configuration
 137  */
 138 #define CONFIG_FTSDMC021
 139
 140 #ifdef CONFIG_FTSDMC021
 141 #include <faraday/ftsdmc021.h>
 142
 143 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
 144                                          FTSDMC021_TP1_TRP(1)   |       \
 145                                          FTSDMC021_TP1_TRCD(1)  |       \
 146                                          FTSDMC021_TP1_TRF(3)   |       \
 147                                          FTSDMC021_TP1_TWR(1)   |       \
 148                                          FTSDMC021_TP1_TCL(2))
 149
 150 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 151                                          FTSDMC021_TP2_INI_REFT(8) |    \
 152                                          FTSDMC021_TP2_REF_INTV(0x180))
 153
 154 /*
 155  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 156  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 157  * C language.
 158  */
 159 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 160                                          FTSDMC021_CR1_DSZ(3)    |      \
 161                                          FTSDMC021_CR1_MBW(2)    |      \
 162                                          FTSDMC021_CR1_BNKSIZE(6))
 163
 164 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 165                                          FTSDMC021_CR2_IREF      |      \
 166                                          FTSDMC021_CR2_ISMR)
 167
 168 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 169 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 170                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 171
 172 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 173         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 174 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
 175                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
 176 #endif
 177
 178 /*
 179  * Physical Memory Map
 180  */
 181 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 182 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 183 #else
 184 #ifdef CONFIG_MEM_REMAP
 185 #define PHYS_SDRAM_0    0x00000000      /* SDRAM Bank #1 */
 186 #else
 187 #define PHYS_SDRAM_0    0x80000000      /* SDRAM Bank #1 */
 188 #endif
 189 #endif
 190
 191 #define PHYS_SDRAM_1 \
 192         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 193
 194 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 195 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 196 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 197 #else
 198 #ifdef CONFIG_MEM_REMAP
 199 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 200 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 201 #else
 202 #define PHYS_SDRAM_0_SIZE       0x08000000      /* 128 MB */
 203 #define PHYS_SDRAM_1_SIZE       0x08000000      /* 128 MB */
 204 #endif
 205 #endif
 206
 207 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 208
 209 #ifdef CONFIG_MEM_REMAP
 210 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 211                                         GENERATED_GBL_DATA_SIZE)
 212 #else
 213 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 214                                         GENERATED_GBL_DATA_SIZE)
 215 #endif /* CONFIG_MEM_REMAP */
 216
 217 /*
 218  * Static memory controller configuration
 219  */
 220 #define CONFIG_FTSMC020
 221
 222 #ifdef CONFIG_FTSMC020
 223 #include <faraday/ftsmc020.h>
 224
 225 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 226         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 227         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 228 }
 229
 230 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 231 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 232                                          FTSMC020_BANK_SIZE_32M |       \
 233                                          FTSMC020_BANK_MBW_32)
 234
 235 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 236                                          FTSMC020_TPR_AST(1)    |       \
 237                                          FTSMC020_TPR_CTW(1)    |       \
 238                                          FTSMC020_TPR_ATI(1)    |       \
 239                                          FTSMC020_TPR_AT2(1)    |       \
 240                                          FTSMC020_TPR_WTC(1)    |       \
 241                                          FTSMC020_TPR_AHT(1)    |       \
 242                                          FTSMC020_TPR_TRNA(1))
 243 #endif
 244
 245 /*
 246  * FLASH on ADP_AG101P is connected to BANK0
 247  * Just disalbe the other BANK to avoid detection error.
 248  */
 249 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 250                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 251                                  FTSMC020_BANK_SIZE_32M           |     \
 252                                  FTSMC020_BANK_MBW_32)
 253
 254 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 255                                  FTSMC020_TPR_CTW(3)   |        \
 256                                  FTSMC020_TPR_ATI(0xf) |        \
 257                                  FTSMC020_TPR_AT2(3)   |        \
 258                                  FTSMC020_TPR_WTC(3)   |        \
 259                                  FTSMC020_TPR_AHT(3)   |        \
 260                                  FTSMC020_TPR_TRNA(0xf))
 261
 262 #define FTSMC020_BANK1_CONFIG   (0x00)
 263 #define FTSMC020_BANK1_TIMING   (0x00)
 264 #endif /* CONFIG_FTSMC020 */
 265
 266 /*
 267  * FLASH and environment organization
 268  */
 269 /* use CFI framework */
 270
 271 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 272 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 273
 274 /* support JEDEC */
 275
 276 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 277 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 278 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 279 #else
 280 #ifdef CONFIG_MEM_REMAP
 281 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 282 #else
 283 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 284 #endif
 285 #endif  /* CONFIG_MEM_REMAP */
 286
 287 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 288 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 289 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 290
 291 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 292 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 293
 294 /* max number of memory banks */
 295 /*
 296  * There are 4 banks supported for this Controller,
 297  * but we have only 1 bank connected to flash on board
 298  */
 299 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 300 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 301 #endif
 302 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 303
 304 /* max number of sectors on one chip */
 305 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 306 #define CONFIG_SYS_MAX_FLASH_SECT       512
 307
 308 /* environments */
 309
 310 /*
 311  * For booting Linux, the board info and command line data
 312  * have to be in the first 16 MB of memory, since this is
 313  * the maximum mapped by the Linux kernel during initialization.
 314  */
 315
 316 /* Initial Memory map for Linux*/
 317 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 318 /* Increase max gunzip size */
 319 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 320
 321 #endif  /* __CONFIG_H */