include/configs/adp-ag101p.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include <asm/arch-ag101/ag101.h>
  13
  14 /*
  15  * CPU and Board Configuration Options
  16  */
  17 #define CONFIG_ADP_AG101P
  18
  19 #define CONFIG_USE_INTERRUPT
  20
  21 #define CONFIG_SKIP_LOWLEVEL_INIT
  22
  23 #define CONFIG_CMDLINE_EDITING
  24
  25 #define CONFIG_SYS_ICACHE_OFF
  26 #define CONFIG_SYS_DCACHE_OFF
  27
  28 #define CONFIG_BOOTP_SEND_HOSTNAME
  29 #define CONFIG_BOOTP_SERVERIP
  30
  31 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  32 #define CONFIG_MEM_REMAP
  33 #endif
  34
  35 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  36 #define CONFIG_SYS_TEXT_BASE    0x00500000
  37 #ifdef CONFIG_OF_CONTROL
  38 #undef CONFIG_OF_SEPARATE
  39 #define CONFIG_OF_EMBED
  40 #endif
  41 #else
  42 #ifdef CONFIG_MEM_REMAP
  43 #define CONFIG_SYS_TEXT_BASE    0x80000000
  44 #else
  45 #define CONFIG_SYS_TEXT_BASE    0x00000000
  46 #endif
  47 #endif
  48
  49 /*
  50  * Timer
  51  */
  52 #define CONFIG_SYS_CLK_FREQ     39062500
  53 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  54
  55 /*
  56  * Use Externel CLOCK or PCLK
  57  */
  58 #undef CONFIG_FTRTC010_EXTCLK
  59
  60 #ifndef CONFIG_FTRTC010_EXTCLK
  61 #define CONFIG_FTRTC010_PCLK
  62 #endif
  63
  64 #ifdef CONFIG_FTRTC010_EXTCLK
  65 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  66 #else
  67 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  68 #endif
  69
  70 #define TIMER_LOAD_VAL  0xffffffff
  71
  72 /*
  73  * Real Time Clock
  74  */
  75 #define CONFIG_RTC_FTRTC010
  76
  77 /*
  78  * Real Time Clock Divider
  79  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  80  */
  81 #define OSC_5MHZ                        (5*1000000)
  82 #define OSC_CLK                         (4*OSC_5MHZ)
  83 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  84
  85 /*
  86  * Serial console configuration
  87  */
  88
  89 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  90 #define CONFIG_CONS_INDEX               1
  91 #define CONFIG_SYS_NS16550_SERIAL
  92 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  93 #ifndef CONFIG_DM_SERIAL
  94 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  95 #endif
  96 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  97
  98 /*
  99  * SD (MMC) controller
 100  */
 101 #define CONFIG_FTSDC010
 102 #define CONFIG_FTSDC010_NUMBER          1
 103 #define CONFIG_FTSDC010_SDIO
 104
 105 /*
 106  * Miscellaneous configurable options
 107  */
 108 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 109
 110 /* Boot Argument Buffer Size */
 111 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 112
 113 /*
 114  * Size of malloc() pool
 115  */
 116 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
 117 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 118
 119 /*
 120  * AHB Controller configuration
 121  */
 122 #define CONFIG_FTAHBC020S
 123
 124 #ifdef CONFIG_FTAHBC020S
 125 #include <faraday/ftahbc020s.h>
 126
 127 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
 128 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
 129
 130 /*
 131  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
 132  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
 133  * in C language.
 134  */
 135 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
 136         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
 137                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 138 #endif
 139
 140 /*
 141  * Watchdog
 142  */
 143 #define CONFIG_FTWDT010_WATCHDOG
 144
 145 /*
 146  * PMU Power controller configuration
 147  */
 148 #define CONFIG_PMU
 149 #define CONFIG_FTPMU010_POWER
 150
 151 #ifdef CONFIG_FTPMU010_POWER
 152 #include <faraday/ftpmu010.h>
 153 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 154 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 155                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 156                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 157                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 158                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 159                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 160                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 161 #endif
 162
 163 /*
 164  * SDRAM controller configuration
 165  */
 166 #define CONFIG_FTSDMC021
 167
 168 #ifdef CONFIG_FTSDMC021
 169 #include <faraday/ftsdmc021.h>
 170
 171 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
 172                                          FTSDMC021_TP1_TRP(1)   |       \
 173                                          FTSDMC021_TP1_TRCD(1)  |       \
 174                                          FTSDMC021_TP1_TRF(3)   |       \
 175                                          FTSDMC021_TP1_TWR(1)   |       \
 176                                          FTSDMC021_TP1_TCL(2))
 177
 178 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 179                                          FTSDMC021_TP2_INI_REFT(8) |    \
 180                                          FTSDMC021_TP2_REF_INTV(0x180))
 181
 182 /*
 183  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 184  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 185  * C language.
 186  */
 187 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 188                                          FTSDMC021_CR1_DSZ(3)    |      \
 189                                          FTSDMC021_CR1_MBW(2)    |      \
 190                                          FTSDMC021_CR1_BNKSIZE(6))
 191
 192 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 193                                          FTSDMC021_CR2_IREF      |      \
 194                                          FTSDMC021_CR2_ISMR)
 195
 196 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 197 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 198                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 199
 200 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 201         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 202 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
 203                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
 204 #endif
 205
 206 /*
 207  * Physical Memory Map
 208  */
 209 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 210 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 211 #else
 212 #ifdef CONFIG_MEM_REMAP
 213 #define PHYS_SDRAM_0    0x00000000      /* SDRAM Bank #1 */
 214 #else
 215 #define PHYS_SDRAM_0    0x80000000      /* SDRAM Bank #1 */
 216 #endif
 217 #endif
 218
 219 #define PHYS_SDRAM_1 \
 220         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 221
 222 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 bank of DRAM */
 223
 224 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 225 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 226 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 227 #else
 228 #ifdef CONFIG_MEM_REMAP
 229 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 230 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 231 #else
 232 #define PHYS_SDRAM_0_SIZE       0x08000000      /* 128 MB */
 233 #define PHYS_SDRAM_1_SIZE       0x08000000      /* 128 MB */
 234 #endif
 235 #endif
 236
 237 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 238
 239 #ifdef CONFIG_MEM_REMAP
 240 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 241                                         GENERATED_GBL_DATA_SIZE)
 242 #else
 243 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 244                                         GENERATED_GBL_DATA_SIZE)
 245 #endif /* CONFIG_MEM_REMAP */
 246
 247 /*
 248  * Load address and memory test area should agree with
 249  * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 250  */
 251 #define CONFIG_SYS_LOAD_ADDR            0x300000
 252
 253 /* memtest works on 63 MB in DRAM */
 254 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
 255 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
 256
 257 /*
 258  * Static memory controller configuration
 259  */
 260 #define CONFIG_FTSMC020
 261
 262 #ifdef CONFIG_FTSMC020
 263 #include <faraday/ftsmc020.h>
 264
 265 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 266         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 267         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 268 }
 269
 270 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 271 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 272                                          FTSMC020_BANK_SIZE_32M |       \
 273                                          FTSMC020_BANK_MBW_32)
 274
 275 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 276                                          FTSMC020_TPR_AST(1)    |       \
 277                                          FTSMC020_TPR_CTW(1)    |       \
 278                                          FTSMC020_TPR_ATI(1)    |       \
 279                                          FTSMC020_TPR_AT2(1)    |       \
 280                                          FTSMC020_TPR_WTC(1)    |       \
 281                                          FTSMC020_TPR_AHT(1)    |       \
 282                                          FTSMC020_TPR_TRNA(1))
 283 #endif
 284
 285 /*
 286  * FLASH on ADP_AG101P is connected to BANK0
 287  * Just disalbe the other BANK to avoid detection error.
 288  */
 289 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 290                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 291                                  FTSMC020_BANK_SIZE_32M           |     \
 292                                  FTSMC020_BANK_MBW_32)
 293
 294 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 295                                  FTSMC020_TPR_CTW(3)   |        \
 296                                  FTSMC020_TPR_ATI(0xf) |        \
 297                                  FTSMC020_TPR_AT2(3)   |        \
 298                                  FTSMC020_TPR_WTC(3)   |        \
 299                                  FTSMC020_TPR_AHT(3)   |        \
 300                                  FTSMC020_TPR_TRNA(0xf))
 301
 302 #define FTSMC020_BANK1_CONFIG   (0x00)
 303 #define FTSMC020_BANK1_TIMING   (0x00)
 304 #endif /* CONFIG_FTSMC020 */
 305
 306 /*
 307  * FLASH and environment organization
 308  */
 309 /* use CFI framework */
 310 #define CONFIG_SYS_FLASH_CFI
 311 #define CONFIG_FLASH_CFI_DRIVER
 312
 313 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 314 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 315 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 316
 317 /* support JEDEC */
 318
 319 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 320 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 321 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 322 #else
 323 #ifdef CONFIG_MEM_REMAP
 324 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 325 #else
 326 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 327 #endif
 328 #endif  /* CONFIG_MEM_REMAP */
 329
 330 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 331 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 332 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 333
 334 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 335 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 336
 337 /* max number of memory banks */
 338 /*
 339  * There are 4 banks supported for this Controller,
 340  * but we have only 1 bank connected to flash on board
 341  */
 342 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 343 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 344 #endif
 345 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 346
 347 /* max number of sectors on one chip */
 348 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 349 #define CONFIG_ENV_SECT_SIZE            CONFIG_FLASH_SECTOR_SIZE
 350 #define CONFIG_SYS_MAX_FLASH_SECT       512
 351
 352 /* environments */
 353 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + 0x140000)
 354 #define CONFIG_ENV_SIZE                 8192
 355 #define CONFIG_ENV_OVERWRITE
 356
 357 /*
 358  * For booting Linux, the board info and command line data
 359  * have to be in the first 16 MB of memory, since this is
 360  * the maximum mapped by the Linux kernel during initialization.
 361  */
 362
 363 /* Initial Memory map for Linux*/
 364 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 365 /* Increase max gunzip size */
 366 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 367
 368 #endif  /* __CONFIG_H */