1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Andes Technology Corporation
4 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
11 #include <asm/arch-ag101/ag101.h>
14 * CPU and Board Configuration Options
16 #define CONFIG_USE_INTERRUPT
18 #define CONFIG_ARCH_MAP_SYSMEM
20 #define CONFIG_BOOTP_SERVERIP
22 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
23 #define CONFIG_MEM_REMAP
26 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
27 #ifdef CONFIG_OF_CONTROL
28 #undef CONFIG_OF_SEPARATE
35 #define CONFIG_SYS_CLK_FREQ 39062500
36 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
39 * Use Externel CLOCK or PCLK
41 #undef CONFIG_FTRTC010_EXTCLK
43 #ifndef CONFIG_FTRTC010_EXTCLK
44 #define CONFIG_FTRTC010_PCLK
47 #ifdef CONFIG_FTRTC010_EXTCLK
48 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
50 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
53 #define TIMER_LOAD_VAL 0xffffffff
58 #define CONFIG_RTC_FTRTC010
61 * Real Time Clock Divider
62 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
64 #define OSC_5MHZ (5*1000000)
65 #define OSC_CLK (4*OSC_5MHZ)
66 #define RTC_DIV_COUNT (0.5) /* Why?? */
69 * Serial console configuration
72 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
73 #define CONFIG_SYS_NS16550_SERIAL
74 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
75 #ifndef CONFIG_DM_SERIAL
76 #define CONFIG_SYS_NS16550_REG_SIZE -4
78 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
81 * Miscellaneous configurable options
85 * AHB Controller configuration
87 #define CONFIG_FTAHBC020S
89 #ifdef CONFIG_FTAHBC020S
90 #include <faraday/ftahbc020s.h>
92 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
93 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
96 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
97 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
100 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
101 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
102 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
108 #define CONFIG_FTWDT010_WATCHDOG
111 * PMU Power controller configuration
114 #define CONFIG_FTPMU010_POWER
116 #ifdef CONFIG_FTPMU010_POWER
117 #include <faraday/ftpmu010.h>
118 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
119 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
120 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
121 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
122 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
123 FTPMU010_SDRAMHTC_CKE_DCSR | \
124 FTPMU010_SDRAMHTC_DQM_DCSR | \
125 FTPMU010_SDRAMHTC_SDCLK_DCSR)
129 * SDRAM controller configuration
131 #define CONFIG_FTSDMC021
133 #ifdef CONFIG_FTSDMC021
134 #include <faraday/ftsdmc021.h>
136 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
137 FTSDMC021_TP1_TRP(1) | \
138 FTSDMC021_TP1_TRCD(1) | \
139 FTSDMC021_TP1_TRF(3) | \
140 FTSDMC021_TP1_TWR(1) | \
141 FTSDMC021_TP1_TCL(2))
143 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
144 FTSDMC021_TP2_INI_REFT(8) | \
145 FTSDMC021_TP2_REF_INTV(0x180))
148 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
149 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
152 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
153 FTSDMC021_CR1_DSZ(3) | \
154 FTSDMC021_CR1_MBW(2) | \
155 FTSDMC021_CR1_BNKSIZE(6))
157 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
158 FTSDMC021_CR2_IREF | \
161 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
162 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
163 CONFIG_SYS_FTSDMC021_BANK0_BASE)
165 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
166 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
167 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
168 CONFIG_SYS_FTSDMC021_BANK1_BASE)
172 * Physical Memory Map
174 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
175 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
177 #ifdef CONFIG_MEM_REMAP
178 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
180 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
184 #define PHYS_SDRAM_1 \
185 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
187 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
188 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
189 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
191 #ifdef CONFIG_MEM_REMAP
192 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
193 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
195 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
196 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
200 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
202 #ifdef CONFIG_MEM_REMAP
203 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
204 GENERATED_GBL_DATA_SIZE)
206 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
207 GENERATED_GBL_DATA_SIZE)
208 #endif /* CONFIG_MEM_REMAP */
211 * Static memory controller configuration
213 #define CONFIG_FTSMC020
215 #ifdef CONFIG_FTSMC020
216 #include <faraday/ftsmc020.h>
218 #define CONFIG_SYS_FTSMC020_CONFIGS { \
219 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
220 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
223 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
224 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
225 FTSMC020_BANK_SIZE_32M | \
226 FTSMC020_BANK_MBW_32)
228 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
229 FTSMC020_TPR_AST(1) | \
230 FTSMC020_TPR_CTW(1) | \
231 FTSMC020_TPR_ATI(1) | \
232 FTSMC020_TPR_AT2(1) | \
233 FTSMC020_TPR_WTC(1) | \
234 FTSMC020_TPR_AHT(1) | \
235 FTSMC020_TPR_TRNA(1))
239 * FLASH on ADP_AG101P is connected to BANK0
240 * Just disalbe the other BANK to avoid detection error.
242 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
243 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
244 FTSMC020_BANK_SIZE_32M | \
245 FTSMC020_BANK_MBW_32)
247 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
248 FTSMC020_TPR_CTW(3) | \
249 FTSMC020_TPR_ATI(0xf) | \
250 FTSMC020_TPR_AT2(3) | \
251 FTSMC020_TPR_WTC(3) | \
252 FTSMC020_TPR_AHT(3) | \
253 FTSMC020_TPR_TRNA(0xf))
255 #define FTSMC020_BANK1_CONFIG (0x00)
256 #define FTSMC020_BANK1_TIMING (0x00)
257 #endif /* CONFIG_FTSMC020 */
260 * FLASH and environment organization
262 /* use CFI framework */
264 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
265 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
269 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
270 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
271 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
273 #ifdef CONFIG_MEM_REMAP
274 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
276 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
278 #endif /* CONFIG_MEM_REMAP */
280 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
281 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
282 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
284 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
285 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
287 /* max number of memory banks */
289 * There are 4 banks supported for this Controller,
290 * but we have only 1 bank connected to flash on board
292 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
293 #define CONFIG_SYS_MAX_FLASH_BANKS 1
295 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
297 /* max number of sectors on one chip */
298 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
299 #define CONFIG_SYS_MAX_FLASH_SECT 512
304 * For booting Linux, the board info and command line data
305 * have to be in the first 16 MB of memory, since this is
306 * the maximum mapped by the Linux kernel during initialization.
309 /* Initial Memory map for Linux*/
310 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
311 /* Increase max gunzip size */
312 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
314 #endif /* __CONFIG_H */