2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch-ag101/ag101.h>
15 * CPU and Board Configuration Options
17 #define CONFIG_ADP_AG101P
19 #define CONFIG_USE_INTERRUPT
21 #define CONFIG_SKIP_LOWLEVEL_INIT
23 #define CONFIG_CMDLINE_EDITING
25 #define CONFIG_SYS_ICACHE_OFF
26 #define CONFIG_SYS_DCACHE_OFF
28 #define CONFIG_BOOTP_SEND_HOSTNAME
29 #define CONFIG_BOOTP_SERVERIP
31 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
32 #define CONFIG_MEM_REMAP
35 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
36 #define CONFIG_SYS_TEXT_BASE 0x00500000
37 #ifdef CONFIG_OF_CONTROL
38 #undef CONFIG_OF_SEPARATE
39 #define CONFIG_OF_EMBED
42 #ifdef CONFIG_MEM_REMAP
43 #define CONFIG_SYS_TEXT_BASE 0x80000000
45 #define CONFIG_SYS_TEXT_BASE 0x00000000
52 #define CONFIG_SYS_CLK_FREQ 39062500
53 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
56 * Use Externel CLOCK or PCLK
58 #undef CONFIG_FTRTC010_EXTCLK
60 #ifndef CONFIG_FTRTC010_EXTCLK
61 #define CONFIG_FTRTC010_PCLK
64 #ifdef CONFIG_FTRTC010_EXTCLK
65 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
67 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
70 #define TIMER_LOAD_VAL 0xffffffff
75 #define CONFIG_RTC_FTRTC010
78 * Real Time Clock Divider
79 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
81 #define OSC_5MHZ (5*1000000)
82 #define OSC_CLK (4*OSC_5MHZ)
83 #define RTC_DIV_COUNT (0.5) /* Why?? */
86 * Serial console configuration
89 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
90 #define CONFIG_CONS_INDEX 1
91 #define CONFIG_SYS_NS16550_SERIAL
92 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
93 #ifndef CONFIG_DM_SERIAL
94 #define CONFIG_SYS_NS16550_REG_SIZE -4
96 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
101 #define CONFIG_FTSDC010
102 #define CONFIG_FTSDC010_NUMBER 1
103 #define CONFIG_FTSDC010_SDIO
106 * Miscellaneous configurable options
108 #define CONFIG_SYS_LONGHELP /* undef to save memory */
110 /* max number of command args */
111 #define CONFIG_SYS_MAXARGS 16
113 /* Boot Argument Buffer Size */
114 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
117 * Size of malloc() pool
119 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
120 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
123 * AHB Controller configuration
125 #define CONFIG_FTAHBC020S
127 #ifdef CONFIG_FTAHBC020S
128 #include <faraday/ftahbc020s.h>
130 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
131 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
134 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
135 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
138 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
139 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
140 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
146 #define CONFIG_FTWDT010_WATCHDOG
149 * PMU Power controller configuration
152 #define CONFIG_FTPMU010_POWER
154 #ifdef CONFIG_FTPMU010_POWER
155 #include <faraday/ftpmu010.h>
156 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
157 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
158 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
159 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
160 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
161 FTPMU010_SDRAMHTC_CKE_DCSR | \
162 FTPMU010_SDRAMHTC_DQM_DCSR | \
163 FTPMU010_SDRAMHTC_SDCLK_DCSR)
167 * SDRAM controller configuration
169 #define CONFIG_FTSDMC021
171 #ifdef CONFIG_FTSDMC021
172 #include <faraday/ftsdmc021.h>
174 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
175 FTSDMC021_TP1_TRP(1) | \
176 FTSDMC021_TP1_TRCD(1) | \
177 FTSDMC021_TP1_TRF(3) | \
178 FTSDMC021_TP1_TWR(1) | \
179 FTSDMC021_TP1_TCL(2))
181 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
182 FTSDMC021_TP2_INI_REFT(8) | \
183 FTSDMC021_TP2_REF_INTV(0x180))
186 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
187 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
190 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
191 FTSDMC021_CR1_DSZ(3) | \
192 FTSDMC021_CR1_MBW(2) | \
193 FTSDMC021_CR1_BNKSIZE(6))
195 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
196 FTSDMC021_CR2_IREF | \
199 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
200 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
201 CONFIG_SYS_FTSDMC021_BANK0_BASE)
203 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
204 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
205 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
206 CONFIG_SYS_FTSDMC021_BANK1_BASE)
210 * Physical Memory Map
212 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
213 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
215 #ifdef CONFIG_MEM_REMAP
216 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
218 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
222 #define PHYS_SDRAM_1 \
223 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
225 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
227 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
228 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
229 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
231 #ifdef CONFIG_MEM_REMAP
232 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
233 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
235 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
236 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
240 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
242 #ifdef CONFIG_MEM_REMAP
243 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
244 GENERATED_GBL_DATA_SIZE)
246 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
247 GENERATED_GBL_DATA_SIZE)
248 #endif /* CONFIG_MEM_REMAP */
251 * Load address and memory test area should agree with
252 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
254 #define CONFIG_SYS_LOAD_ADDR 0x300000
256 /* memtest works on 63 MB in DRAM */
257 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
258 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
261 * Static memory controller configuration
263 #define CONFIG_FTSMC020
265 #ifdef CONFIG_FTSMC020
266 #include <faraday/ftsmc020.h>
268 #define CONFIG_SYS_FTSMC020_CONFIGS { \
269 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
270 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
273 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
274 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
275 FTSMC020_BANK_SIZE_32M | \
276 FTSMC020_BANK_MBW_32)
278 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
279 FTSMC020_TPR_AST(1) | \
280 FTSMC020_TPR_CTW(1) | \
281 FTSMC020_TPR_ATI(1) | \
282 FTSMC020_TPR_AT2(1) | \
283 FTSMC020_TPR_WTC(1) | \
284 FTSMC020_TPR_AHT(1) | \
285 FTSMC020_TPR_TRNA(1))
289 * FLASH on ADP_AG101P is connected to BANK0
290 * Just disalbe the other BANK to avoid detection error.
292 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
293 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
294 FTSMC020_BANK_SIZE_32M | \
295 FTSMC020_BANK_MBW_32)
297 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
298 FTSMC020_TPR_CTW(3) | \
299 FTSMC020_TPR_ATI(0xf) | \
300 FTSMC020_TPR_AT2(3) | \
301 FTSMC020_TPR_WTC(3) | \
302 FTSMC020_TPR_AHT(3) | \
303 FTSMC020_TPR_TRNA(0xf))
305 #define FTSMC020_BANK1_CONFIG (0x00)
306 #define FTSMC020_BANK1_TIMING (0x00)
307 #endif /* CONFIG_FTSMC020 */
310 * FLASH and environment organization
312 /* use CFI framework */
313 #define CONFIG_SYS_FLASH_CFI
314 #define CONFIG_FLASH_CFI_DRIVER
316 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
317 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
318 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
322 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
323 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
324 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
326 #ifdef CONFIG_MEM_REMAP
327 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
329 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
331 #endif /* CONFIG_MEM_REMAP */
333 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
334 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
335 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
337 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
338 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
340 /* max number of memory banks */
342 * There are 4 banks supported for this Controller,
343 * but we have only 1 bank connected to flash on board
345 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
346 #define CONFIG_SYS_MAX_FLASH_BANKS 1
348 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
350 /* max number of sectors on one chip */
351 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
352 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
353 #define CONFIG_SYS_MAX_FLASH_SECT 512
356 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
357 #define CONFIG_ENV_SIZE 8192
358 #define CONFIG_ENV_OVERWRITE
361 * For booting Linux, the board info and command line data
362 * have to be in the first 16 MB of memory, since this is
363 * the maximum mapped by the Linux kernel during initialization.
366 /* Initial Memory map for Linux*/
367 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
368 /* Increase max gunzip size */
369 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
371 #endif /* __CONFIG_H */