6085208a5d93f5b0d935be0fa664007e8fae807d
[platform/kernel/u-boot.git] / include / configs / adp-ag101p.h
1 /*
2  * Copyright (C) 2011 Andes Technology Corporation
3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  */
23
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 #include <asm/arch/ag101.h>
28
29 /*
30  * CPU and Board Configuration Options
31  */
32 #define CONFIG_ADP_AG101P
33
34 #define CONFIG_USE_INTERRUPT
35
36 #define CONFIG_SKIP_LOWLEVEL_INIT
37
38 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
39 #define CONFIG_MEM_REMAP
40 #endif
41
42 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
43 #define CONFIG_SYS_TEXT_BASE    0x03200000
44 #else
45 #define CONFIG_SYS_TEXT_BASE    0x00000000
46 #endif
47
48 /*
49  * Timer
50  */
51
52 /*
53  * According to the discussion in u-boot mailing list before,
54  * CONFIG_SYS_HZ at 1000 is mandatory.
55  */
56 #define CONFIG_SYS_HZ           1000
57 #define CONFIG_SYS_CLK_FREQ     39062500
58 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
59
60 /*
61  * Use Externel CLOCK or PCLK
62  */
63 #undef CONFIG_FTRTC010_EXTCLK
64
65 #ifndef CONFIG_FTRTC010_EXTCLK
66 #define CONFIG_FTRTC010_PCLK
67 #endif
68
69 #ifdef CONFIG_FTRTC010_EXTCLK
70 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
71 #else
72 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
73 #endif
74
75 #define TIMER_LOAD_VAL  0xffffffff
76
77 /*
78  * Real Time Clock
79  */
80 #define CONFIG_RTC_FTRTC010
81
82 /*
83  * Real Time Clock Divider
84  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
85  */
86 #define OSC_5MHZ                        (5*1000000)
87 #define OSC_CLK                         (4*OSC_5MHZ)
88 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
89
90 /*
91  * Serial console configuration
92  */
93
94 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
95 #define CONFIG_BAUDRATE                 38400
96 #define CONFIG_CONS_INDEX               1
97 #define CONFIG_SYS_NS16550
98 #define CONFIG_SYS_NS16550_SERIAL
99 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
100 #define CONFIG_SYS_NS16550_REG_SIZE     -4
101 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
102
103 /*
104  * Ethernet
105  */
106 #define CONFIG_FTMAC100
107
108 #define CONFIG_BOOTDELAY        3
109
110 /*
111  * SD (MMC) controller
112  */
113 #define CONFIG_MMC
114 #define CONFIG_CMD_MMC
115 #define CONFIG_GENERIC_MMC
116 #define CONFIG_DOS_PARTITION
117 #define CONFIG_FTSDC010
118 #define CONFIG_FTSDC010_NUMBER          1
119 #define CONFIG_FTSDC010_SDIO
120 #define CONFIG_CMD_FAT
121 #define CONFIG_CMD_EXT2
122
123 /*
124  * Command line configuration.
125  */
126 #include <config_cmd_default.h>
127
128 #define CONFIG_CMD_CACHE
129 #define CONFIG_CMD_DATE
130 #define CONFIG_CMD_PING
131
132 /*
133  * Miscellaneous configurable options
134  */
135 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
136 #define CONFIG_SYS_PROMPT       "NDS32 # "      /* Monitor Command Prompt */
137 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
138
139 /* Print Buffer Size */
140 #define CONFIG_SYS_PBSIZE       \
141         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
142
143 /* max number of command args */
144 #define CONFIG_SYS_MAXARGS      16
145
146 /* Boot Argument Buffer Size */
147 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
148
149 /*
150  * Size of malloc() pool
151  */
152 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
153 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
154
155 /*
156  * size in bytes reserved for initial data
157  */
158 #define CONFIG_SYS_GBL_DATA_SIZE        128
159
160 /*
161  * AHB Controller configuration
162  */
163 #define CONFIG_FTAHBC020S
164
165 #ifdef CONFIG_FTAHBC020S
166 #include <faraday/ftahbc020s.h>
167
168 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
169 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
170
171 /*
172  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
173  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
174  * in C language.
175  */
176 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
177         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
178                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
179 #endif
180
181 /*
182  * Watchdog
183  */
184 #define CONFIG_FTWDT010_WATCHDOG
185
186 /*
187  * PMU Power controller configuration
188  */
189 #define CONFIG_PMU
190 #define CONFIG_FTPMU010_POWER
191
192 #ifdef CONFIG_FTPMU010_POWER
193 #include <faraday/ftpmu010.h>
194 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
195 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
196                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
197                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
198                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
199                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
200                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
201                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
202 #endif
203
204 /*
205  * SDRAM controller configuration
206  */
207 #define CONFIG_FTSDMC021
208
209 #ifdef CONFIG_FTSDMC021
210 #include <faraday/ftsdmc021.h>
211
212 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
213                                          FTSDMC021_TP1_TRP(1)   |       \
214                                          FTSDMC021_TP1_TRCD(1)  |       \
215                                          FTSDMC021_TP1_TRF(3)   |       \
216                                          FTSDMC021_TP1_TWR(1)   |       \
217                                          FTSDMC021_TP1_TCL(2))
218
219 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
220                                          FTSDMC021_TP2_INI_REFT(8) |    \
221                                          FTSDMC021_TP2_REF_INTV(0x180))
222
223 /*
224  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
225  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
226  * C language.
227  */
228 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
229                                          FTSDMC021_CR1_DSZ(3)    |      \
230                                          FTSDMC021_CR1_MBW(2)    |      \
231                                          FTSDMC021_CR1_BNKSIZE(6))
232
233 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
234                                          FTSDMC021_CR2_IREF      |      \
235                                          FTSDMC021_CR2_ISMR)
236
237 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
238 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
239                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
240
241 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
242         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
243 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
244                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
245 #endif
246
247 /*
248  * Physical Memory Map
249  */
250 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
251 #define PHYS_SDRAM_0            0x00000000      /* SDRAM Bank #1 */
252 #if defined(CONFIG_MEM_REMAP)
253 #define PHYS_SDRAM_0_AT_INIT    0x10000000      /* SDRAM Bank #1 before remap*/
254 #endif
255 #else   /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
256 #define PHYS_SDRAM_0            0x10000000      /* SDRAM Bank #1 */
257 #endif
258 #define PHYS_SDRAM_1 \
259         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
260
261 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 bank of DRAM */
262 #define PHYS_SDRAM_0_SIZE       0x04000000      /* 64 MB */
263 #define PHYS_SDRAM_1_SIZE       0x04000000      /* 64 MB */
264
265 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
266
267 #ifdef CONFIG_MEM_REMAP
268 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
269                                         GENERATED_GBL_DATA_SIZE)
270 #else
271 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
272                                         GENERATED_GBL_DATA_SIZE)
273 #endif /* CONFIG_MEM_REMAP */
274
275 /*
276  * Load address and memory test area should agree with
277  * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
278  */
279 #define CONFIG_SYS_LOAD_ADDR            0x300000
280
281 /* memtest works on 63 MB in DRAM */
282 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
283 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
284
285 /*
286  * Static memory controller configuration
287  */
288 #define CONFIG_FTSMC020
289
290 #ifdef CONFIG_FTSMC020
291 #include <faraday/ftsmc020.h>
292
293 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
294         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
295         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
296 }
297
298 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
299 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
300                                          FTSMC020_BANK_SIZE_32M |       \
301                                          FTSMC020_BANK_MBW_32)
302
303 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
304                                          FTSMC020_TPR_AST(1)    |       \
305                                          FTSMC020_TPR_CTW(1)    |       \
306                                          FTSMC020_TPR_ATI(1)    |       \
307                                          FTSMC020_TPR_AT2(1)    |       \
308                                          FTSMC020_TPR_WTC(1)    |       \
309                                          FTSMC020_TPR_AHT(1)    |       \
310                                          FTSMC020_TPR_TRNA(1))
311 #endif
312
313 /*
314  * FLASH on ADP_AG101P is connected to BANK0
315  * Just disalbe the other BANK to avoid detection error.
316  */
317 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
318                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
319                                  FTSMC020_BANK_SIZE_32M           |     \
320                                  FTSMC020_BANK_MBW_32)
321
322 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
323                                  FTSMC020_TPR_CTW(3)   |        \
324                                  FTSMC020_TPR_ATI(0xf) |        \
325                                  FTSMC020_TPR_AT2(3)   |        \
326                                  FTSMC020_TPR_WTC(3)   |        \
327                                  FTSMC020_TPR_AHT(3)   |        \
328                                  FTSMC020_TPR_TRNA(0xf))
329
330 #define FTSMC020_BANK1_CONFIG   (0x00)
331 #define FTSMC020_BANK1_TIMING   (0x00)
332 #endif /* CONFIG_FTSMC020 */
333
334 /*
335  * FLASH and environment organization
336  */
337 /* use CFI framework */
338 #define CONFIG_SYS_FLASH_CFI
339 #define CONFIG_FLASH_CFI_DRIVER
340
341 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
342 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
343
344 /* support JEDEC */
345
346 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
347 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
348 #define PHYS_FLASH_1                    0x80400000      /* BANK 1 */
349 #else   /* !CONFIG_SKIP_LOWLEVEL_INIT */
350 #ifdef CONFIG_MEM_REMAP
351 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
352 #else
353 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
354 #endif  /* CONFIG_MEM_REMAP */
355 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
356
357 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
358 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
359 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
360
361 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
362 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
363
364 /* max number of memory banks */
365 /*
366  * There are 4 banks supported for this Controller,
367  * but we have only 1 bank connected to flash on board
368  */
369 #define CONFIG_SYS_MAX_FLASH_BANKS      1
370
371 /* max number of sectors on one chip */
372 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2*2)
373 #define CONFIG_ENV_SECT_SIZE            CONFIG_FLASH_SECTOR_SIZE
374 #define CONFIG_SYS_MAX_FLASH_SECT       128
375
376 /* environments */
377 #define CONFIG_ENV_IS_IN_FLASH
378 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + 0x140000)
379 #define CONFIG_ENV_SIZE                 8192
380 #define CONFIG_ENV_OVERWRITE
381
382 #endif  /* __CONFIG_H */