Merge git://git.denx.de/u-boot-dm
[platform/kernel/u-boot.git] / include / configs / adp-ag101.h
1 /*
2  * Copyright (C) 2011 Andes Technology Corporation
3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 #include <asm/arch/ag101.h>
13
14 /*
15  * CPU and Board Configuration Options
16  */
17 #define CONFIG_ADP_AG101
18
19 #define CONFIG_USE_INTERRUPT
20
21 #define CONFIG_SKIP_LOWLEVEL_INIT
22
23 /*
24  * Definitions related to passing arguments to kernel.
25  */
26 #define CONFIG_CMDLINE_TAG                      /* send commandline to Kernel */
27 #define CONFIG_SETUP_MEMORY_TAGS        /* send memory definition to kernel */
28 #define CONFIG_INITRD_TAG                       /* send initrd params */
29
30 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
31 #define CONFIG_MEM_REMAP
32 #endif
33
34 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
35 #define CONFIG_SYS_TEXT_BASE    0x03200000
36 #else
37 #define CONFIG_SYS_TEXT_BASE    0x00000000
38 #endif
39
40 /*
41  * Timer
42  */
43 #define CONFIG_SYS_CLK_FREQ     48000000
44 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
45
46 /*
47  * Use Externel CLOCK or PCLK
48  */
49 #undef CONFIG_FTRTC010_EXTCLK
50
51 #ifndef CONFIG_FTRTC010_EXTCLK
52 #define CONFIG_FTRTC010_PCLK
53 #endif
54
55 #ifdef CONFIG_FTRTC010_EXTCLK
56 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
57 #else
58 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
59 #endif
60
61 #define TIMER_LOAD_VAL  0xffffffff
62
63 /*
64  * Real Time Clock
65  */
66 #define CONFIG_RTC_FTRTC010
67
68 /*
69  * Real Time Clock Divider
70  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
71  */
72 #define OSC_5MHZ                        (5*1000000)
73 #define OSC_CLK                         (2*OSC_5MHZ)
74 #define RTC_DIV_COUNT                   (OSC_CLK/OSC_5MHZ)
75
76 /*
77  * Serial console configuration
78  */
79
80 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
81 #define CONFIG_BAUDRATE                 38400
82 #define CONFIG_CONS_INDEX               1
83 #define CONFIG_SYS_NS16550
84 #define CONFIG_SYS_NS16550_SERIAL
85 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
86 #define CONFIG_SYS_NS16550_REG_SIZE     -4
87 #define CONFIG_SYS_NS16550_CLK          ((46080000 * 20) / 25)  /* AG101 */
88
89 /*
90  * Ethernet
91  */
92 #define CONFIG_FTMAC100
93
94 #define CONFIG_BOOTDELAY        3
95
96 /*
97  * SD (MMC) controller
98  */
99 #define CONFIG_MMC
100 #define CONFIG_CMD_MMC
101 #define CONFIG_GENERIC_MMC
102 #define CONFIG_DOS_PARTITION
103 #define CONFIG_FTSDC010
104 #define CONFIG_FTSDC010_NUMBER          1
105 #define CONFIG_FTSDC010_SDIO
106 #define CONFIG_CMD_FAT
107 #define CONFIG_CMD_EXT2
108
109 /*
110  * Command line configuration.
111  */
112 #include <config_cmd_default.h>
113
114 #define CONFIG_CMD_CACHE
115 #define CONFIG_CMD_DATE
116 #define CONFIG_CMD_PING
117
118 /*
119  * Miscellaneous configurable options
120  */
121 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
122 #define CONFIG_SYS_PROMPT       "NDS32 # "      /* Monitor Command Prompt */
123 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
124
125 /* Print Buffer Size */
126 #define CONFIG_SYS_PBSIZE       \
127         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
128
129 /* max number of command args */
130 #define CONFIG_SYS_MAXARGS      16
131
132 /* Boot Argument Buffer Size */
133 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
134
135 /*
136  * Size of malloc() pool
137  */
138 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
139 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
140
141 /*
142  * AHB Controller configuration
143  */
144 #define CONFIG_FTAHBC020S
145
146 #ifdef CONFIG_FTAHBC020S
147 #include <faraday/ftahbc020s.h>
148
149 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
150 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
151
152 /*
153  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
154  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
155  * in C language.
156  */
157 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
158         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
159                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
160 #endif
161
162 /*
163  * Watchdog
164  */
165 #define CONFIG_FTWDT010_WATCHDOG
166
167 /*
168  * PMU Power controller configuration
169  */
170 #define CONFIG_PMU
171 #define CONFIG_FTPMU010_POWER
172
173 #ifdef CONFIG_FTPMU010_POWER
174 #include <faraday/ftpmu010.h>
175 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
176 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
177                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
178                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
179                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
180                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
181                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
182                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
183 #endif
184
185 /*
186  * SDRAM controller configuration
187  */
188 #define CONFIG_FTSDMC021
189
190 #ifdef CONFIG_FTSDMC021
191 #include <faraday/ftsdmc021.h>
192
193 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRP(1)   |       \
194                                          FTSDMC021_TP1_TRCD(1)  |       \
195                                          FTSDMC021_TP1_TRF(3)   |       \
196                                          FTSDMC021_TP1_TWR(1)   |       \
197                                          FTSDMC021_TP1_TCL(2))
198
199 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
200                                          FTSDMC021_TP2_INI_REFT(8) |    \
201                                          FTSDMC021_TP2_REF_INTV(0x180))
202
203 /*
204  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
205  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
206  * C language.
207  */
208 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
209                                          FTSDMC021_CR1_DSZ(3)    |      \
210                                          FTSDMC021_CR1_MBW(2)    |      \
211                                          FTSDMC021_CR1_BNKSIZE(6))
212
213 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
214                                          FTSDMC021_CR2_IREF      |      \
215                                          FTSDMC021_CR2_ISMR)
216
217 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
218 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
219                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
220
221 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
222         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
223 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE   |      \
224                 CONFIG_SYS_FTSDMC021_BANK1_BASE)
225
226 #endif
227
228 /*
229  * Physical Memory Map
230  */
231 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
232 #define PHYS_SDRAM_0            0x00000000      /* SDRAM Bank #1 */
233 #if defined(CONFIG_MEM_REMAP)
234 #define PHYS_SDRAM_0_AT_INIT    0x10000000      /* SDRAM Bank #1 before remap*/
235 #endif
236 #else   /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
237 #define PHYS_SDRAM_0            0x10000000      /* SDRAM Bank #1 */
238 #endif
239 #define PHYS_SDRAM_1 \
240         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
241
242 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 bank of DRAM */
243 #define PHYS_SDRAM_0_SIZE       0x04000000      /* 64 MB */
244 #define PHYS_SDRAM_1_SIZE       0x04000000      /* 64 MB */
245
246 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
247
248 #ifdef CONFIG_MEM_REMAP
249 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
250                                         GENERATED_GBL_DATA_SIZE)
251 #else
252 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
253                                         GENERATED_GBL_DATA_SIZE)
254 #endif /* CONFIG_MEM_REMAP */
255
256 /*
257  * Load address and memory test area should agree with
258  * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
259  */
260 #define CONFIG_SYS_LOAD_ADDR            0x300000
261
262 /* memtest works on 63 MB in DRAM */
263 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
264 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
265
266 /*
267  * Static memory controller configuration
268  */
269 #define CONFIG_FTSMC020
270
271 #ifdef CONFIG_FTSMC020
272 #include <faraday/ftsmc020.h>
273
274 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
275 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
276         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
277         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
278 }
279 #else
280 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
281         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
282 }
283 #endif
284
285 /*
286  * There are 2 bank connected to FTSMC020 on ADP-AG101.
287  * You can use jumper and switch to force it booted from ROM or FLASH.
288  * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
289  * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
290  */
291 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
292 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
293                                          FTSMC020_BANK_SIZE_32M |       \
294                                          FTSMC020_BANK_MBW_32)
295
296 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
297                                          FTSMC020_TPR_AST(1)    |       \
298                                          FTSMC020_TPR_CTW(1)    |       \
299                                          FTSMC020_TPR_ATI(1)    |       \
300                                          FTSMC020_TPR_AT2(1)    |       \
301                                          FTSMC020_TPR_WTC(1)    |       \
302                                          FTSMC020_TPR_AHT(1)    |       \
303                                          FTSMC020_TPR_TRNA(1))
304 #endif
305
306 /*
307  * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
308  * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
309  *    Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
310  * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
311  */
312 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_SIZE_32M           |     \
313                                  FTSMC020_BANK_MBW_32)
314
315 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_RBE      |        \
316                                  FTSMC020_TPR_AST(3)   |        \
317                                  FTSMC020_TPR_CTW(3)   |        \
318                                  FTSMC020_TPR_ATI(0xf) |        \
319                                  FTSMC020_TPR_AT2(3)   |        \
320                                  FTSMC020_TPR_WTC(3)   |        \
321                                  FTSMC020_TPR_AHT(3)   |        \
322                                  FTSMC020_TPR_TRNA(0xf))
323
324 #define FTSMC020_BANK1_CONFIG   (FTSMC020_BANK_ENABLE   |       \
325                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
326                                  FTSMC020_BANK_SIZE_32M |       \
327                                  FTSMC020_BANK_MBW_32)
328
329 #define FTSMC020_BANK1_TIMING   (FTSMC020_TPR_RBE       |       \
330                                  FTSMC020_TPR_AST(1)    |       \
331                                  FTSMC020_TPR_CTW(1)    |       \
332                                  FTSMC020_TPR_ATI(1)    |       \
333                                  FTSMC020_TPR_AT2(1)    |       \
334                                  FTSMC020_TPR_WTC(1)    |       \
335                                  FTSMC020_TPR_AHT(1)    |       \
336                                  FTSMC020_TPR_TRNA(1))
337 #endif /* CONFIG_FTSMC020 */
338
339 /*
340  * FLASH and environment organization
341  */
342 /* use CFI framework */
343 #define CONFIG_SYS_FLASH_CFI
344 #define CONFIG_FLASH_CFI_DRIVER
345
346 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
347 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
348
349 /* support JEDEC */
350
351 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
352 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
353 #define PHYS_FLASH_1                    0x80400000      /* BANK 1 */
354 #else   /* !CONFIG_SKIP_LOWLEVEL_INIT */
355 #ifdef CONFIG_MEM_REMAP
356 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
357 #else
358 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
359 #endif  /* CONFIG_MEM_REMAP */
360 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
361
362 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
363 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
364 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
365
366 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
367 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
368
369 /* max number of memory banks */
370 /*
371  * There are 4 banks supported for this Controller,
372  * but we have only 1 bank connected to flash on board
373  */
374 #define CONFIG_SYS_MAX_FLASH_BANKS      1
375
376 /* max number of sectors on one chip */
377 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2*2)
378 #define CONFIG_ENV_SECT_SIZE            CONFIG_FLASH_SECTOR_SIZE
379 #define CONFIG_SYS_MAX_FLASH_SECT       128
380
381 /* environments */
382 #define CONFIG_ENV_IS_IN_FLASH
383 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + 0x40000)
384 #define CONFIG_ENV_SIZE                 8192
385 #define CONFIG_ENV_OVERWRITE
386
387 #endif  /* __CONFIG_H */