2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch-ae3xx/ae3xx.h>
15 * CPU and Board Configuration Options
17 #define CONFIG_USE_INTERRUPT
19 #define CONFIG_SKIP_LOWLEVEL_INIT
21 #define CONFIG_SKIP_TRUNOFF_WATCHDOG
23 #define CONFIG_CMDLINE_EDITING
24 #define CONFIG_PANIC_HANG
26 #define CONFIG_SYS_ICACHE_OFF
27 #define CONFIG_SYS_DCACHE_OFF
29 #define CONFIG_BOOTP_SEND_HOSTNAME
30 #define CONFIG_BOOTP_SERVERIP
32 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
33 #define CONFIG_SYS_TEXT_BASE 0x00500000
34 #ifdef CONFIG_OF_CONTROL
35 #undef CONFIG_OF_SEPARATE
36 #define CONFIG_OF_EMBED
40 #define CONFIG_SYS_TEXT_BASE 0x80000000
46 #define CONFIG_SYS_CLK_FREQ 39062500
47 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
50 * Use Externel CLOCK or PCLK
52 #undef CONFIG_FTRTC010_EXTCLK
54 #ifndef CONFIG_FTRTC010_EXTCLK
55 #define CONFIG_FTRTC010_PCLK
58 #ifdef CONFIG_FTRTC010_EXTCLK
59 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
61 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
64 #define TIMER_LOAD_VAL 0xffffffff
69 #define CONFIG_RTC_FTRTC010
72 * Real Time Clock Divider
73 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
75 #define OSC_5MHZ (5*1000000)
76 #define OSC_CLK (4*OSC_5MHZ)
77 #define RTC_DIV_COUNT (0.5) /* Why?? */
80 * Serial console configuration
83 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
84 #define CONFIG_CONS_INDEX 1
85 #define CONFIG_SYS_NS16550_SERIAL
86 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
87 #ifndef CONFIG_DM_SERIAL
88 #define CONFIG_SYS_NS16550_REG_SIZE -4
90 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
95 #define CONFIG_FTMAC100
100 #define CONFIG_FTSDC010
101 #define CONFIG_FTSDC010_NUMBER 1
102 #define CONFIG_FTSDC010_SDIO
105 * Miscellaneous configurable options
107 #define CONFIG_SYS_LONGHELP /* undef to save memory */
108 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
110 /* Print Buffer Size */
111 #define CONFIG_SYS_PBSIZE \
112 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
114 /* max number of command args */
115 #define CONFIG_SYS_MAXARGS 16
117 /* Boot Argument Buffer Size */
118 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
121 * Size of malloc() pool
123 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
124 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
127 * Physical Memory Map
129 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
131 #define PHYS_SDRAM_1 \
132 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
134 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
136 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
137 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
139 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
141 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
142 GENERATED_GBL_DATA_SIZE)
145 * Load address and memory test area should agree with
146 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
148 #define CONFIG_SYS_LOAD_ADDR 0x300000
150 /* memtest works on 63 MB in DRAM */
151 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
152 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
155 * Static memory controller configuration
157 #define CONFIG_FTSMC020
159 #ifdef CONFIG_FTSMC020
160 #include <faraday/ftsmc020.h>
162 #define CONFIG_SYS_FTSMC020_CONFIGS { \
163 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
164 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
167 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
168 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
169 FTSMC020_BANK_SIZE_32M | \
170 FTSMC020_BANK_MBW_32)
172 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
173 FTSMC020_TPR_AST(1) | \
174 FTSMC020_TPR_CTW(1) | \
175 FTSMC020_TPR_ATI(1) | \
176 FTSMC020_TPR_AT2(1) | \
177 FTSMC020_TPR_WTC(1) | \
178 FTSMC020_TPR_AHT(1) | \
179 FTSMC020_TPR_TRNA(1))
183 * FLASH on ADP_AG101P is connected to BANK0
184 * Just disalbe the other BANK to avoid detection error.
186 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
187 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
188 FTSMC020_BANK_SIZE_32M | \
189 FTSMC020_BANK_MBW_32)
191 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
192 FTSMC020_TPR_CTW(3) | \
193 FTSMC020_TPR_ATI(0xf) | \
194 FTSMC020_TPR_AT2(3) | \
195 FTSMC020_TPR_WTC(3) | \
196 FTSMC020_TPR_AHT(3) | \
197 FTSMC020_TPR_TRNA(0xf))
199 #define FTSMC020_BANK1_CONFIG (0x00)
200 #define FTSMC020_BANK1_TIMING (0x00)
201 #endif /* CONFIG_FTSMC020 */
204 * FLASH and environment organization
206 /* use CFI framework */
207 #define CONFIG_SYS_FLASH_CFI
208 #define CONFIG_FLASH_CFI_DRIVER
210 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
211 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
212 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
215 #ifdef CONFIG_CFI_FLASH
216 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
219 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
220 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */
221 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
222 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
223 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
225 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
226 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
228 /* max number of memory banks */
230 * There are 4 banks supported for this Controller,
231 * but we have only 1 bank connected to flash on board
233 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
234 #define CONFIG_SYS_MAX_FLASH_BANKS 1
236 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
238 /* max number of sectors on one chip */
239 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
240 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
241 #define CONFIG_SYS_MAX_FLASH_SECT 512
244 #define CONFIG_ENV_IS_IN_FLASH
245 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
246 #define CONFIG_ENV_SIZE 8192
247 #define CONFIG_ENV_OVERWRITE
250 * For booting Linux, the board info and command line data
251 * have to be in the first 16 MB of memory, since this is
252 * the maximum mapped by the Linux kernel during initialization.
255 /* Initial Memory map for Linux*/
256 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
257 /* Increase max gunzip size */
258 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
260 #endif /* __CONFIG_H */