1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Andes Technology Corporation
4 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
11 #include <asm/arch-ae3xx/ae3xx.h>
14 * CPU and Board Configuration Options
16 #define CONFIG_USE_INTERRUPT
18 #define CONFIG_SKIP_TRUNOFF_WATCHDOG
20 #define CONFIG_ARCH_MAP_SYSMEM
22 #define CONFIG_BOOTP_SERVERIP
24 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
25 #ifdef CONFIG_OF_CONTROL
26 #undef CONFIG_OF_SEPARATE
27 #define CONFIG_OF_EMBED
34 #define CONFIG_SYS_CLK_FREQ 39062500
35 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
38 * Use Externel CLOCK or PCLK
40 #undef CONFIG_FTRTC010_EXTCLK
42 #ifndef CONFIG_FTRTC010_EXTCLK
43 #define CONFIG_FTRTC010_PCLK
46 #ifdef CONFIG_FTRTC010_EXTCLK
47 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
49 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
52 #define TIMER_LOAD_VAL 0xffffffff
57 #define CONFIG_RTC_FTRTC010
60 * Real Time Clock Divider
61 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
63 #define OSC_5MHZ (5*1000000)
64 #define OSC_CLK (4*OSC_5MHZ)
65 #define RTC_DIV_COUNT (0.5) /* Why?? */
68 * Serial console configuration
71 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
72 #define CONFIG_SYS_NS16550_SERIAL
73 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
74 #ifndef CONFIG_DM_SERIAL
75 #define CONFIG_SYS_NS16550_REG_SIZE -4
77 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
80 * Miscellaneous configurable options
84 * Size of malloc() pool
86 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
91 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
93 #define PHYS_SDRAM_1 \
94 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
96 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
97 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
99 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
101 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
102 GENERATED_GBL_DATA_SIZE)
105 * Static memory controller configuration
107 #define CONFIG_FTSMC020
109 #ifdef CONFIG_FTSMC020
110 #include <faraday/ftsmc020.h>
112 #define CONFIG_SYS_FTSMC020_CONFIGS { \
113 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
114 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
117 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
118 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
119 FTSMC020_BANK_SIZE_32M | \
120 FTSMC020_BANK_MBW_32)
122 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
123 FTSMC020_TPR_AST(1) | \
124 FTSMC020_TPR_CTW(1) | \
125 FTSMC020_TPR_ATI(1) | \
126 FTSMC020_TPR_AT2(1) | \
127 FTSMC020_TPR_WTC(1) | \
128 FTSMC020_TPR_AHT(1) | \
129 FTSMC020_TPR_TRNA(1))
133 * FLASH on ADP_AG101P is connected to BANK0
134 * Just disalbe the other BANK to avoid detection error.
136 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
137 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
138 FTSMC020_BANK_SIZE_32M | \
139 FTSMC020_BANK_MBW_32)
141 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
142 FTSMC020_TPR_CTW(3) | \
143 FTSMC020_TPR_ATI(0xf) | \
144 FTSMC020_TPR_AT2(3) | \
145 FTSMC020_TPR_WTC(3) | \
146 FTSMC020_TPR_AHT(3) | \
147 FTSMC020_TPR_TRNA(0xf))
149 #define FTSMC020_BANK1_CONFIG (0x00)
150 #define FTSMC020_BANK1_TIMING (0x00)
151 #endif /* CONFIG_FTSMC020 */
154 * FLASH and environment organization
156 /* use CFI framework */
158 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
159 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
162 #ifdef CONFIG_CFI_FLASH
163 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
166 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
167 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */
168 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
169 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
170 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
172 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
175 /* max number of memory banks */
177 * There are 4 banks supported for this Controller,
178 * but we have only 1 bank connected to flash on board
180 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
181 #define CONFIG_SYS_MAX_FLASH_BANKS 1
183 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
185 /* max number of sectors on one chip */
186 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
187 #define CONFIG_SYS_MAX_FLASH_SECT 512
195 * For booting Linux, the board info and command line data
196 * have to be in the first 16 MB of memory, since this is
197 * the maximum mapped by the Linux kernel during initialization.
200 /* Initial Memory map for Linux*/
201 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
202 /* Increase max gunzip size */
203 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
205 #endif /* __CONFIG_H */