include/configs/adp-ae3xx.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch-ae3xx/ae3xx.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_USE_INTERRUPT
  17
  18 #define CONFIG_SKIP_LOWLEVEL_INIT
  19
  20 #define CONFIG_SKIP_TRUNOFF_WATCHDOG
  21
  22 #define CONFIG_ARCH_MAP_SYSMEM
  23
  24 #define CONFIG_BOOTP_SERVERIP
  25
  26 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  27 #ifdef CONFIG_OF_CONTROL
  28 #undef CONFIG_OF_SEPARATE
  29 #define CONFIG_OF_EMBED
  30 #endif
  31 #endif
  32
  33 /*
  34  * Timer
  35  */
  36 #define CONFIG_SYS_CLK_FREQ     39062500
  37 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  38
  39 /*
  40  * Use Externel CLOCK or PCLK
  41  */
  42 #undef CONFIG_FTRTC010_EXTCLK
  43
  44 #ifndef CONFIG_FTRTC010_EXTCLK
  45 #define CONFIG_FTRTC010_PCLK
  46 #endif
  47
  48 #ifdef CONFIG_FTRTC010_EXTCLK
  49 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  50 #else
  51 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  52 #endif
  53
  54 #define TIMER_LOAD_VAL  0xffffffff
  55
  56 /*
  57  * Real Time Clock
  58  */
  59 #define CONFIG_RTC_FTRTC010
  60
  61 /*
  62  * Real Time Clock Divider
  63  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  64  */
  65 #define OSC_5MHZ                        (5*1000000)
  66 #define OSC_CLK                         (4*OSC_5MHZ)
  67 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  68
  69 /*
  70  * Serial console configuration
  71  */
  72
  73 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  74 #define CONFIG_SYS_NS16550_SERIAL
  75 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  76 #ifndef CONFIG_DM_SERIAL
  77 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  78 #endif
  79 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  80
  81 /*
  82  * Miscellaneous configurable options
  83  */
  84
  85 /*
  86  * Size of malloc() pool
  87  */
  88 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  89 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
  90
  91 /*
  92  * Physical Memory Map
  93  */
  94 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
  95
  96 #define PHYS_SDRAM_1 \
  97         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
  98
  99 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 100 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 101
 102 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 103
 104 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 105                                         GENERATED_GBL_DATA_SIZE)
 106
 107 /*
 108  * Load address and memory test area should agree with
 109  * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 110  */
 111 #define CONFIG_SYS_LOAD_ADDR            0x300000
 112
 113 /* memtest works on 63 MB in DRAM */
 114
 115 /*
 116  * Static memory controller configuration
 117  */
 118 #define CONFIG_FTSMC020
 119
 120 #ifdef CONFIG_FTSMC020
 121 #include <faraday/ftsmc020.h>
 122
 123 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 124         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 125         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 126 }
 127
 128 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 129 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 130                                          FTSMC020_BANK_SIZE_32M |       \
 131                                          FTSMC020_BANK_MBW_32)
 132
 133 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 134                                          FTSMC020_TPR_AST(1)    |       \
 135                                          FTSMC020_TPR_CTW(1)    |       \
 136                                          FTSMC020_TPR_ATI(1)    |       \
 137                                          FTSMC020_TPR_AT2(1)    |       \
 138                                          FTSMC020_TPR_WTC(1)    |       \
 139                                          FTSMC020_TPR_AHT(1)    |       \
 140                                          FTSMC020_TPR_TRNA(1))
 141 #endif
 142
 143 /*
 144  * FLASH on ADP_AG101P is connected to BANK0
 145  * Just disalbe the other BANK to avoid detection error.
 146  */
 147 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 148                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 149                                  FTSMC020_BANK_SIZE_32M           |     \
 150                                  FTSMC020_BANK_MBW_32)
 151
 152 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 153                                  FTSMC020_TPR_CTW(3)   |        \
 154                                  FTSMC020_TPR_ATI(0xf) |        \
 155                                  FTSMC020_TPR_AT2(3)   |        \
 156                                  FTSMC020_TPR_WTC(3)   |        \
 157                                  FTSMC020_TPR_AHT(3)   |        \
 158                                  FTSMC020_TPR_TRNA(0xf))
 159
 160 #define FTSMC020_BANK1_CONFIG   (0x00)
 161 #define FTSMC020_BANK1_TIMING   (0x00)
 162 #endif /* CONFIG_FTSMC020 */
 163
 164 /*
 165  * FLASH and environment organization
 166  */
 167 /* use CFI framework */
 168
 169 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 170 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 171
 172 /* support JEDEC */
 173 #ifdef CONFIG_CFI_FLASH
 174 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       1
 175 #endif
 176
 177 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 178 #define PHYS_FLASH_1                    0x88000000      /* BANK 0 */
 179 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 180 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 181 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 182
 183 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 184 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 185
 186 /* max number of memory banks */
 187 /*
 188  * There are 4 banks supported for this Controller,
 189  * but we have only 1 bank connected to flash on board
 190  */
 191 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 192 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 193 #endif
 194 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 195
 196 /* max number of sectors on one chip */
 197 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 198 #define CONFIG_SYS_MAX_FLASH_SECT       512
 199
 200 /* environments */
 201
 202
 203 /* SPI FLASH */
 204
 205 /*
 206  * For booting Linux, the board info and command line data
 207  * have to be in the first 16 MB of memory, since this is
 208  * the maximum mapped by the Linux kernel during initialization.
 209  */
 210
 211 /* Initial Memory map for Linux*/
 212 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 213 /* Increase max gunzip size */
 214 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 215
 216 #endif  /* __CONFIG_H */