include/configs/adp-ae3xx.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch-ae3xx/ae3xx.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_USE_INTERRUPT
  17
  18 #define CONFIG_SKIP_TRUNOFF_WATCHDOG
  19
  20 #define CONFIG_ARCH_MAP_SYSMEM
  21
  22 #define CONFIG_BOOTP_SERVERIP
  23
  24 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  25 #ifdef CONFIG_OF_CONTROL
  26 #undef CONFIG_OF_SEPARATE
  27 #endif
  28 #endif
  29
  30 /*
  31  * Timer
  32  */
  33 #define CONFIG_SYS_CLK_FREQ     39062500
  34 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  35
  36 /*
  37  * Use Externel CLOCK or PCLK
  38  */
  39 #undef CONFIG_FTRTC010_EXTCLK
  40
  41 #ifndef CONFIG_FTRTC010_EXTCLK
  42 #define CONFIG_FTRTC010_PCLK
  43 #endif
  44
  45 #ifdef CONFIG_FTRTC010_EXTCLK
  46 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  47 #else
  48 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  49 #endif
  50
  51 #define TIMER_LOAD_VAL  0xffffffff
  52
  53 /*
  54  * Real Time Clock
  55  */
  56 #define CONFIG_RTC_FTRTC010
  57
  58 /*
  59  * Real Time Clock Divider
  60  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  61  */
  62 #define OSC_5MHZ                        (5*1000000)
  63 #define OSC_CLK                         (4*OSC_5MHZ)
  64 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  65
  66 /*
  67  * Serial console configuration
  68  */
  69
  70 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  71 #define CONFIG_SYS_NS16550_SERIAL
  72 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  73 #ifndef CONFIG_DM_SERIAL
  74 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  75 #endif
  76 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  77
  78 /*
  79  * Miscellaneous configurable options
  80  */
  81
  82 /*
  83  * Size of malloc() pool
  84  */
  85 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  86
  87 /*
  88  * Physical Memory Map
  89  */
  90 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
  91
  92 #define PHYS_SDRAM_1 \
  93         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
  94
  95 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
  96 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
  97
  98 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
  99
 100 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 101                                         GENERATED_GBL_DATA_SIZE)
 102
 103 /*
 104  * Static memory controller configuration
 105  */
 106 #define CONFIG_FTSMC020
 107
 108 #ifdef CONFIG_FTSMC020
 109 #include <faraday/ftsmc020.h>
 110
 111 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 112         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 113         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 114 }
 115
 116 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 117 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 118                                          FTSMC020_BANK_SIZE_32M |       \
 119                                          FTSMC020_BANK_MBW_32)
 120
 121 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 122                                          FTSMC020_TPR_AST(1)    |       \
 123                                          FTSMC020_TPR_CTW(1)    |       \
 124                                          FTSMC020_TPR_ATI(1)    |       \
 125                                          FTSMC020_TPR_AT2(1)    |       \
 126                                          FTSMC020_TPR_WTC(1)    |       \
 127                                          FTSMC020_TPR_AHT(1)    |       \
 128                                          FTSMC020_TPR_TRNA(1))
 129 #endif
 130
 131 /*
 132  * FLASH on ADP_AG101P is connected to BANK0
 133  * Just disalbe the other BANK to avoid detection error.
 134  */
 135 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 136                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 137                                  FTSMC020_BANK_SIZE_32M           |     \
 138                                  FTSMC020_BANK_MBW_32)
 139
 140 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 141                                  FTSMC020_TPR_CTW(3)   |        \
 142                                  FTSMC020_TPR_ATI(0xf) |        \
 143                                  FTSMC020_TPR_AT2(3)   |        \
 144                                  FTSMC020_TPR_WTC(3)   |        \
 145                                  FTSMC020_TPR_AHT(3)   |        \
 146                                  FTSMC020_TPR_TRNA(0xf))
 147
 148 #define FTSMC020_BANK1_CONFIG   (0x00)
 149 #define FTSMC020_BANK1_TIMING   (0x00)
 150 #endif /* CONFIG_FTSMC020 */
 151
 152 /*
 153  * FLASH and environment organization
 154  */
 155 /* use CFI framework */
 156
 157 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 158 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 159
 160 /* support JEDEC */
 161 #ifdef CONFIG_CFI_FLASH
 162 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       1
 163 #endif
 164
 165 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 166 #define PHYS_FLASH_1                    0x88000000      /* BANK 0 */
 167 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 168 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 169 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 170
 171 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 172 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 173
 174 /* max number of memory banks */
 175 /*
 176  * There are 4 banks supported for this Controller,
 177  * but we have only 1 bank connected to flash on board
 178  */
 179 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 180 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 181 #endif
 182 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 183
 184 /* max number of sectors on one chip */
 185 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 186 #define CONFIG_SYS_MAX_FLASH_SECT       512
 187
 188 /* environments */
 189
 190
 191 /* SPI FLASH */
 192
 193 /*
 194  * For booting Linux, the board info and command line data
 195  * have to be in the first 16 MB of memory, since this is
 196  * the maximum mapped by the Linux kernel during initialization.
 197  */
 198
 199 /* Initial Memory map for Linux*/
 200 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 201 /* Increase max gunzip size */
 202 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 203
 204 #endif  /* __CONFIG_H */