include/configs/adp-ae3xx.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch-ae3xx/ae3xx.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_USE_INTERRUPT
  17
  18 #define CONFIG_SKIP_TRUNOFF_WATCHDOG
  19
  20 #define CONFIG_BOOTP_SERVERIP
  21
  22 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  23 #ifdef CONFIG_OF_CONTROL
  24 #undef CONFIG_OF_SEPARATE
  25 #endif
  26 #endif
  27
  28 /*
  29  * Timer
  30  */
  31 #define VERSION_CLOCK           get_board_sys_clk()
  32
  33 /*
  34  * Use Externel CLOCK or PCLK
  35  */
  36 #undef CONFIG_FTRTC010_EXTCLK
  37
  38 #ifndef CONFIG_FTRTC010_EXTCLK
  39 #define CONFIG_FTRTC010_PCLK
  40 #endif
  41
  42 #ifdef CONFIG_FTRTC010_EXTCLK
  43 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  44 #else
  45 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  46 #endif
  47
  48 #define TIMER_LOAD_VAL  0xffffffff
  49
  50 /*
  51  * Real Time Clock
  52  */
  53 #define CONFIG_RTC_FTRTC010
  54
  55 /*
  56  * Real Time Clock Divider
  57  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  58  */
  59 #define OSC_5MHZ                        (5*1000000)
  60 #define OSC_CLK                         (4*OSC_5MHZ)
  61 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  62
  63 /*
  64  * Serial console configuration
  65  */
  66
  67 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  68 #define CONFIG_SYS_NS16550_SERIAL
  69 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  70 #ifndef CONFIG_DM_SERIAL
  71 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  72 #endif
  73 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  74
  75 /*
  76  * Miscellaneous configurable options
  77  */
  78
  79 /*
  80  * Size of malloc() pool
  81  */
  82 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  83
  84 /*
  85  * Physical Memory Map
  86  */
  87 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
  88
  89 #define PHYS_SDRAM_1 \
  90         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
  91
  92 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
  93 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
  94
  95 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
  96
  97 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
  98                                         GENERATED_GBL_DATA_SIZE)
  99
 100 /*
 101  * Static memory controller configuration
 102  */
 103 #define CONFIG_FTSMC020
 104
 105 #ifdef CONFIG_FTSMC020
 106 #include <faraday/ftsmc020.h>
 107
 108 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 109         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 110         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 111 }
 112
 113 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 114 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 115                                          FTSMC020_BANK_SIZE_32M |       \
 116                                          FTSMC020_BANK_MBW_32)
 117
 118 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 119                                          FTSMC020_TPR_AST(1)    |       \
 120                                          FTSMC020_TPR_CTW(1)    |       \
 121                                          FTSMC020_TPR_ATI(1)    |       \
 122                                          FTSMC020_TPR_AT2(1)    |       \
 123                                          FTSMC020_TPR_WTC(1)    |       \
 124                                          FTSMC020_TPR_AHT(1)    |       \
 125                                          FTSMC020_TPR_TRNA(1))
 126 #endif
 127
 128 /*
 129  * FLASH on ADP_AG101P is connected to BANK0
 130  * Just disalbe the other BANK to avoid detection error.
 131  */
 132 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 133                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 134                                  FTSMC020_BANK_SIZE_32M           |     \
 135                                  FTSMC020_BANK_MBW_32)
 136
 137 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 138                                  FTSMC020_TPR_CTW(3)   |        \
 139                                  FTSMC020_TPR_ATI(0xf) |        \
 140                                  FTSMC020_TPR_AT2(3)   |        \
 141                                  FTSMC020_TPR_WTC(3)   |        \
 142                                  FTSMC020_TPR_AHT(3)   |        \
 143                                  FTSMC020_TPR_TRNA(0xf))
 144
 145 #define FTSMC020_BANK1_CONFIG   (0x00)
 146 #define FTSMC020_BANK1_TIMING   (0x00)
 147 #endif /* CONFIG_FTSMC020 */
 148
 149 /*
 150  * FLASH and environment organization
 151  */
 152 /* use CFI framework */
 153
 154 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 155 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 156
 157 /* support JEDEC */
 158 #ifdef CONFIG_CFI_FLASH
 159 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       1
 160 #endif
 161
 162 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 163 #define PHYS_FLASH_1                    0x88000000      /* BANK 0 */
 164 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 165 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 166 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 167
 168 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 169 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 170
 171 /* max number of memory banks */
 172 /*
 173  * There are 4 banks supported for this Controller,
 174  * but we have only 1 bank connected to flash on board
 175  */
 176 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 177 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 178 #endif
 179 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 180
 181 /* max number of sectors on one chip */
 182 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 183 #define CONFIG_SYS_MAX_FLASH_SECT       512
 184
 185 /* environments */
 186
 187
 188 /* SPI FLASH */
 189
 190 /*
 191  * For booting Linux, the board info and command line data
 192  * have to be in the first 16 MB of memory, since this is
 193  * the maximum mapped by the Linux kernel during initialization.
 194  */
 195
 196 /* Initial Memory map for Linux*/
 197 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 198 /* Increase max gunzip size */
 199 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 200
 201 #endif  /* __CONFIG_H */