include/configs/adp-ae3xx.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include <asm/arch-ae3xx/ae3xx.h>
  13
  14 /*
  15  * CPU and Board Configuration Options
  16  */
  17 #define CONFIG_USE_INTERRUPT
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 #define CONFIG_SKIP_TRUNOFF_WATCHDOG
  22
  23 #define CONFIG_ARCH_MAP_SYSMEM
  24
  25 #define CONFIG_BOOTP_SEND_HOSTNAME
  26 #define CONFIG_BOOTP_SERVERIP
  27
  28 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  29 #ifdef CONFIG_OF_CONTROL
  30 #undef CONFIG_OF_SEPARATE
  31 #define CONFIG_OF_EMBED
  32 #endif
  33 #endif
  34
  35 /*
  36  * Timer
  37  */
  38 #define CONFIG_SYS_CLK_FREQ     39062500
  39 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  40
  41 /*
  42  * Use Externel CLOCK or PCLK
  43  */
  44 #undef CONFIG_FTRTC010_EXTCLK
  45
  46 #ifndef CONFIG_FTRTC010_EXTCLK
  47 #define CONFIG_FTRTC010_PCLK
  48 #endif
  49
  50 #ifdef CONFIG_FTRTC010_EXTCLK
  51 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  52 #else
  53 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  54 #endif
  55
  56 #define TIMER_LOAD_VAL  0xffffffff
  57
  58 /*
  59  * Real Time Clock
  60  */
  61 #define CONFIG_RTC_FTRTC010
  62
  63 /*
  64  * Real Time Clock Divider
  65  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  66  */
  67 #define OSC_5MHZ                        (5*1000000)
  68 #define OSC_CLK                         (4*OSC_5MHZ)
  69 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  70
  71 /*
  72  * Serial console configuration
  73  */
  74
  75 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  76 #define CONFIG_SYS_NS16550_SERIAL
  77 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  78 #ifndef CONFIG_DM_SERIAL
  79 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  80 #endif
  81 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  82
  83 /*
  84  * SD (MMC) controller
  85  */
  86 #define CONFIG_FTSDC010_SDIO
  87
  88 /*
  89  * Miscellaneous configurable options
  90  */
  91
  92 /*
  93  * Size of malloc() pool
  94  */
  95 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  96 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
  97
  98 /*
  99  * Physical Memory Map
 100  */
 101 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 102
 103 #define PHYS_SDRAM_1 \
 104         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 105
 106 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 bank of DRAM */
 107
 108 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 109 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 110
 111 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 112
 113 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 114                                         GENERATED_GBL_DATA_SIZE)
 115
 116 /*
 117  * Load address and memory test area should agree with
 118  * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 119  */
 120 #define CONFIG_SYS_LOAD_ADDR            0x300000
 121
 122 /* memtest works on 63 MB in DRAM */
 123 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
 124 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
 125
 126 /*
 127  * Static memory controller configuration
 128  */
 129 #define CONFIG_FTSMC020
 130
 131 #ifdef CONFIG_FTSMC020
 132 #include <faraday/ftsmc020.h>
 133
 134 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 135         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 136         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 137 }
 138
 139 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 140 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 141                                          FTSMC020_BANK_SIZE_32M |       \
 142                                          FTSMC020_BANK_MBW_32)
 143
 144 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 145                                          FTSMC020_TPR_AST(1)    |       \
 146                                          FTSMC020_TPR_CTW(1)    |       \
 147                                          FTSMC020_TPR_ATI(1)    |       \
 148                                          FTSMC020_TPR_AT2(1)    |       \
 149                                          FTSMC020_TPR_WTC(1)    |       \
 150                                          FTSMC020_TPR_AHT(1)    |       \
 151                                          FTSMC020_TPR_TRNA(1))
 152 #endif
 153
 154 /*
 155  * FLASH on ADP_AG101P is connected to BANK0
 156  * Just disalbe the other BANK to avoid detection error.
 157  */
 158 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 159                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 160                                  FTSMC020_BANK_SIZE_32M           |     \
 161                                  FTSMC020_BANK_MBW_32)
 162
 163 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 164                                  FTSMC020_TPR_CTW(3)   |        \
 165                                  FTSMC020_TPR_ATI(0xf) |        \
 166                                  FTSMC020_TPR_AT2(3)   |        \
 167                                  FTSMC020_TPR_WTC(3)   |        \
 168                                  FTSMC020_TPR_AHT(3)   |        \
 169                                  FTSMC020_TPR_TRNA(0xf))
 170
 171 #define FTSMC020_BANK1_CONFIG   (0x00)
 172 #define FTSMC020_BANK1_TIMING   (0x00)
 173 #endif /* CONFIG_FTSMC020 */
 174
 175 /*
 176  * FLASH and environment organization
 177  */
 178 /* use CFI framework */
 179 #define CONFIG_SYS_FLASH_CFI
 180 #define CONFIG_FLASH_CFI_DRIVER
 181
 182 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 183 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 184 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 185
 186 /* support JEDEC */
 187 #ifdef CONFIG_CFI_FLASH
 188 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       1
 189 #endif
 190
 191 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 192 #define PHYS_FLASH_1                    0x88000000      /* BANK 0 */
 193 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 194 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 195 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 196
 197 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 198 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 199
 200 /* max number of memory banks */
 201 /*
 202  * There are 4 banks supported for this Controller,
 203  * but we have only 1 bank connected to flash on board
 204  */
 205 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 206 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 207 #endif
 208 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 209
 210 /* max number of sectors on one chip */
 211 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 212 #define CONFIG_SYS_MAX_FLASH_SECT       512
 213
 214 /* environments */
 215 #define CONFIG_ENV_SPI_BUS              0
 216 #define CONFIG_ENV_SPI_CS               0
 217 #define CONFIG_ENV_SPI_MAX_HZ           50000000
 218 #define CONFIG_ENV_SPI_MODE             0
 219 #define CONFIG_ENV_SECT_SIZE            0x1000
 220 #define CONFIG_ENV_OFFSET               0x140000
 221 #define CONFIG_ENV_SIZE                 8192
 222 #define CONFIG_ENV_OVERWRITE
 223
 224
 225 /* SPI FLASH */
 226 #define CONFIG_SF_DEFAULT_BUS           0
 227 #define CONFIG_SF_DEFAULT_CS            0
 228 #define CONFIG_SF_DEFAULT_SPEED         1000000
 229 #define CONFIG_SF_DEFAULT_MODE          0
 230
 231 /*
 232  * For booting Linux, the board info and command line data
 233  * have to be in the first 16 MB of memory, since this is
 234  * the maximum mapped by the Linux kernel during initialization.
 235  */
 236
 237 /* Initial Memory map for Linux*/
 238 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 239 /* Increase max gunzip size */
 240 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 241
 242 #endif  /* __CONFIG_H */