include/configs/ac14xx.h

   1 /*
   2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
   3  * (C) Copyright 2010 DAVE Srl <www.dave.eu>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * ifm AC14xx (MPC5121e based) board configuration file
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #define CONFIG_AC14XX 1
  16 /*
  17  * Memory map for the ifm AC14xx board:
  18  *
  19  * 0x0000_0000-0x0FFF_FFFF      DDR RAM (256 MB)
  20  * 0x3000_0000-0x3001_FFFF      On Chip SRAM (128 KB)
  21  * 0x8000_0000-0x803F_FFFF      IMMR (4 MB)
  22  * 0xE000_0000-0xEFFF_FFFF      several LPB attached hardware (CSx)
  23  * 0xFC00_0000-0xFFFF_FFFF      NOR Boot FLASH (64 MB)
  24  */
  25
  26 /*
  27  * High Level Configuration Options
  28  */
  29 #define CONFIG_E300             1       /* E300 Family */
  30
  31 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  32
  33 #if defined(CONFIG_VIDEO)
  34 #define CONFIG_CFB_CONSOLE
  35 #define CONFIG_VGA_AS_SINGLE_DEVICE
  36 #endif
  37
  38 #define CONFIG_SYS_MPC512X_CLKIN        25000000        /* in Hz */
  39 #define SCFR1_IPS_DIV                   2
  40 #define SCFR1_LPC_DIV                   2
  41 #define SCFR1_NFC_DIV                   2
  42 #define SCFR1_DIU_DIV                   240
  43
  44 #define CONFIG_MISC_INIT_R
  45
  46 #define CONFIG_SYS_IMMR                 0x80000000
  47 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR + 0x2100)
  48
  49 /* more aggressive 'mtest' over a wider address range */
  50 #define CONFIG_SYS_ALT_MEMTEST
  51 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest region */
  52 #define CONFIG_SYS_MEMTEST_END          0x0FE00000
  53
  54 /*
  55  * DDR Setup - manually set all parameters as there's no SPD etc.
  56  */
  57 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  58 #define CONFIG_SYS_DDR_BASE             0x00000000
  59 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  60 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
  61
  62 /*
  63  * DDR Controller Configuration
  64  *
  65  * SYS_CFG:
  66  *      [31:31] MDDRC Soft Reset:       Diabled
  67  *      [30:30] DRAM CKE pin:           Enabled
  68  *      [29:29] DRAM CLK:               Enabled
  69  *      [28:28] Command Mode:           Enabled (For initialization only)
  70  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  71  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  72  *      [20:19] Read Test:              DON'T USE
  73  *      [18:18] Self Refresh:           Enabled
  74  *      [17:17] 16bit Mode:             Disabled
  75  *      [16:13] Ready Delay:            2
  76  *      [12:12] Half DQS Delay:         Disabled
  77  *      [11:11] Quarter DQS Delay:      Disabled
  78  *      [10:08] Write Delay:            2
  79  *      [07:07] Early ODT:              Disabled
  80  *      [06:06] On DIE Termination:     Disabled
  81  *      [05:05] FIFO Overflow Clear:    DON'T USE here
  82  *      [04:04] FIFO Underflow Clear:   DON'T USE here
  83  *      [03:03] FIFO Overflow Pending:  DON'T USE here
  84  *      [02:02] FIFO Underlfow Pending: DON'T USE here
  85  *      [01:01] FIFO Overlfow Enabled:  Enabled
  86  *      [00:00] FIFO Underflow Enabled: Enabled
  87  * TIME_CFG0
  88  *      [31:16] DRAM Refresh Time:      0 CSB clocks
  89  *      [15:8]  DRAM Command Time:      0 CSB clocks
  90  *      [07:00] DRAM Precharge Time:    0 CSB clocks
  91  * TIME_CFG1
  92  *      [31:26] DRAM tRFC:
  93  *      [25:21] DRAM tWR1:
  94  *      [20:17] DRAM tWRT1:
  95  *      [16:11] DRAM tDRR:
  96  *      [10:05] DRAM tRC:
  97  *      [04:00] DRAM tRAS:
  98  * TIME_CFG2
  99  *      [31:28] DRAM tRCD:
 100  *      [27:23] DRAM tFAW:
 101  *      [22:19] DRAM tRTW1:
 102  *      [18:15] DRAM tCCD:
 103  *      [14:10] DRAM tRTP:
 104  *      [09:05] DRAM tRP:
 105  *      [04:00] DRAM tRPA
 106  */
 107
 108 /*
 109  * NOTE: although this board uses DDR1 only, the common source brings defaults
 110  * for DDR2 init sequences, that's why we have to keep those here as well
 111  */
 112
 113 /* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
 114 #define CONFIG_SYS_IOCTRL_MUX_DDR       ((0 << 6) | (3 << 3) | (3 << 0))
 115
 116 #define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
 117                         | (1 << 31)     /* RST_B */ \
 118                         | (1 << 30)     /* CKE */ \
 119                         | (1 << 29)     /* CLK_ON */ \
 120                         | (0 << 28)     /* CMD_MODE */ \
 121                         | (5 << 25)     /* DRAM_ROW_SELECT */ \
 122                         | (5 << 21)     /* DRAM_BANK_SELECT */ \
 123                         | (0 << 18)     /* SELF_REF_EN */ \
 124                         | (0 << 17)     /* 16BIT_MODE */ \
 125                         | (4 << 13)     /* RDLY */ \
 126                         | (1 << 12)     /* HALF_DQS_DLY */ \
 127                         | (0 << 11)     /* QUART_DQS_DLY */ \
 128                         | (1 <<  8)     /* WDLY */ \
 129                         | (0 <<  7)     /* EARLY_ODT */ \
 130                         | (0 <<  6)     /* ON_DIE_TERMINATE */ \
 131                         | (0 <<  5)     /* FIFO_OV_CLEAR */ \
 132                         | (0 <<  4)     /* FIFO_UV_CLEAR */ \
 133                         | (0 <<  1)     /* FIFO_OV_EN */ \
 134                         | (0 <<  0)     /* FIFO_UV_EN */ \
 135                         )
 136
 137 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x04E03124
 138 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x30CA1147
 139 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x32B10864
 140
 141 /* register address only, i.e. template without values */
 142 #define CONFIG_SYS_MICRON_BMODE         0x01000000
 143 #define CONFIG_SYS_MICRON_EMODE         0x01010000
 144 #define CONFIG_SYS_MICRON_EMODE2        0x01020000
 145 #define CONFIG_SYS_MICRON_EMODE3        0x01030000
 146 /*
 147  * values for mode registers (without mode register address)
 148  */
 149 /* CAS 2.5 (6), burst seq (0) and length 4 (2) */
 150 #define CONFIG_SYS_MICRON_BMODE_PARAM   0x00000062
 151 #define CONFIG_SYS_MICRON_BMODE_RSTDLL  0x00000100
 152 /* DLL enable, reduced drive strength */
 153 #define CONFIG_SYS_MICRON_EMODE_PARAM   0x00000002
 154
 155 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 156 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 157 #define CONFIG_SYS_MICRON_EMR          ((1 << 24) |     /* CMD_REQ */ \
 158                                         (0 << 22) |     /* DRAM_CS */ \
 159                                         (0 << 21) |     /* DRAM_RAS */ \
 160                                         (0 << 20) |     /* DRAM_CAS */ \
 161                                         (0 << 19) |     /* DRAM_WEB */ \
 162                                         (1 << 16) |     /* DRAM_BS[2:0] */ \
 163                                         (0 << 15) |     /* */ \
 164                                         (0 << 12) |     /* A12->out */ \
 165                                         (0 << 11) |     /* A11->RDQS */ \
 166                                         (0 << 10) |     /* A10->DQS# */ \
 167                                         (0 <<  7) |     /* OCD program */ \
 168                                         (0 <<  6) |     /* Rtt1 */ \
 169                                         (0 <<  3) |     /* posted CAS# */ \
 170                                         (0 <<  2) |     /* Rtt0 */ \
 171                                         (1 <<  1) |     /* ODS */ \
 172                                         (0 <<  0)       /* DLL */ \
 173                                      )
 174 #define CONFIG_SYS_MICRON_EMR2          0x01020000
 175 #define CONFIG_SYS_MICRON_EMR3          0x01030000
 176 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 177 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
 178 #define CONFIG_SYS_MICRON_EMR_OCD      ((1 << 24) |     /* CMD_REQ */ \
 179                                         (0 << 22) |     /* DRAM_CS */ \
 180                                         (0 << 21) |     /* DRAM_RAS */ \
 181                                         (0 << 20) |     /* DRAM_CAS */ \
 182                                         (0 << 19) |     /* DRAM_WEB */ \
 183                                         (1 << 16) |     /* DRAM_BS[2:0] */ \
 184                                         (0 << 15) |     /* */ \
 185                                         (0 << 12) |     /* A12->out */ \
 186                                         (0 << 11) |     /* A11->RDQS */ \
 187                                         (1 << 10) |     /* A10->DQS# */ \
 188                                         (7 <<  7) |     /* OCD program */ \
 189                                         (0 <<  6) |     /* Rtt1 */ \
 190                                         (0 <<  3) |     /* posted CAS# */ \
 191                                         (1 <<  2) |     /* Rtt0 */ \
 192                                         (0 <<  1) |     /* ODS */ \
 193                                         (0 <<  0)       /* DLL */ \
 194                                      )
 195
 196 /*
 197  * Backward compatible definitions,
 198  * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
 199  */
 200 #define CONFIG_SYS_DDRCMD_EM2           (CONFIG_SYS_MICRON_EMR2)
 201 #define CONFIG_SYS_DDRCMD_EM3           (CONFIG_SYS_MICRON_EMR3)
 202 #define CONFIG_SYS_DDRCMD_EN_DLL        (CONFIG_SYS_MICRON_EMR)
 203 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   (CONFIG_SYS_MICRON_EMR_OCD)
 204
 205 /* DDR Priority Manager Configuration */
 206 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 207 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 208 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 209 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 210 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 211 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 212 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 213 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 214 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 215 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 216 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 217 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 218 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 219 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 220 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 221 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 222 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 223 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 224 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 225 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 226 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 227 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 228 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 229
 230 /*
 231  * NOR FLASH on the Local Bus
 232  */
 233 #define CONFIG_SYS_FLASH_CFI                            /* use the CFI code */
 234 #define CONFIG_FLASH_CFI_DRIVER                         /* use the CFI driver */
 235 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of FLASH */
 236 #define CONFIG_SYS_FLASH_SIZE           0x04000000      /* max flash size */
 237
 238 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 239 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 240 #define CONFIG_SYS_FLASH_BANKS_LIST     { \
 241         CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
 242         }
 243 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
 244
 245 #undef CONFIG_SYS_FLASH_CHECKSUM
 246 #define CONFIG_SYS_FLASH_PROTECTION
 247
 248 /*
 249  * SRAM support
 250  */
 251 #define CONFIG_SYS_SRAM_BASE            0x30000000
 252 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 253
 254 /*
 255  * CS related parameters
 256  */
 257 /* CS0 Flash */
 258 #define CONFIG_SYS_CS0_CFG              0x00031110
 259 #define CONFIG_SYS_CS0_START            0xFC000000
 260 #define CONFIG_SYS_CS0_SIZE             0x04000000
 261 /* CS1 FRAM */
 262 #define CONFIG_SYS_CS1_CFG              0x00011000
 263 #define CONFIG_SYS_CS1_START            0xE0000000
 264 #define CONFIG_SYS_CS1_SIZE             0x00010000
 265 /* CS2 AS-i 1 */
 266 #define CONFIG_SYS_CS2_CFG              0x00009100
 267 #define CONFIG_SYS_CS2_START            0xE0100000
 268 #define CONFIG_SYS_CS2_SIZE             0x00080000
 269 /* CS3 netX */
 270 #define CONFIG_SYS_CS3_CFG              0x000A1140
 271 #define CONFIG_SYS_CS3_START            0xE0300000
 272 #define CONFIG_SYS_CS3_SIZE             0x00020000
 273 /* CS5 safety */
 274 #define CONFIG_SYS_CS5_CFG              0x0011F000
 275 #define CONFIG_SYS_CS5_START            0xE0400000
 276 #define CONFIG_SYS_CS5_SIZE             0x00010000
 277 /* CS6 AS-i 2 */
 278 #define CONFIG_SYS_CS6_CFG              0x00009100
 279 #define CONFIG_SYS_CS6_START            0xE0200000
 280 #define CONFIG_SYS_CS6_SIZE             0x00080000
 281
 282 /* Don't use alternative CS timing for any CS */
 283 #define CONFIG_SYS_CS_ALETIMING         0x00000000
 284 #define CONFIG_SYS_CS_BURST             0x00000000
 285 #define CONFIG_SYS_CS_DEADCYCLE         0x00000020
 286 #define CONFIG_SYS_CS_HOLDCYCLE         0x00000020
 287
 288 /* Use SRAM for initial stack */
 289 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE
 290 #define CONFIG_SYS_INIT_RAM_END         CONFIG_SYS_SRAM_SIZE
 291
 292 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - \
 293                                          GENERATED_GBL_DATA_SIZE)
 294 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 295
 296 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 297 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
 298
 299 #ifdef  CONFIG_FSL_DIU_FB
 300 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)
 301 #else
 302 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 303 #endif
 304
 305 /*
 306  * Serial Port
 307  */
 308 #define CONFIG_CONS_INDEX               1
 309
 310 /*
 311  * Serial console configuration
 312  */
 313 #define CONFIG_PSC_CONSOLE              3       /* console on PSC3 */
 314 #define CONFIG_SYS_PSC3
 315 #if CONFIG_PSC_CONSOLE != 3
 316 #error CONFIG_PSC_CONSOLE must be 3
 317 #endif
 318
 319 #define CONFIG_BAUDRATE                 115200  /* ... at 115200 bps */
 320
 321 #define CONSOLE_FIFO_TX_SIZE            FIFOC_PSC3_TX_SIZE
 322 #define CONSOLE_FIFO_TX_ADDR            FIFOC_PSC3_TX_ADDR
 323 #define CONSOLE_FIFO_RX_SIZE            FIFOC_PSC3_RX_SIZE
 324 #define CONSOLE_FIFO_RX_ADDR            FIFOC_PSC3_RX_ADDR
 325
 326 /*
 327  * Clocks in use
 328  */
 329 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |           \
 330                          CLOCK_SCCR1_LPC_EN |           \
 331                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
 332                          CLOCK_SCCR1_PSC_EN(7) |        \
 333                          CLOCK_SCCR1_PSCFIFO_EN |       \
 334                          CLOCK_SCCR1_DDR_EN |           \
 335                          CLOCK_SCCR1_FEC_EN |           \
 336                          CLOCK_SCCR1_TPR_EN)
 337
 338 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |           \
 339                          CLOCK_SCCR2_SPDIF_EN |         \
 340                          CLOCK_SCCR2_DIU_EN |           \
 341                          CLOCK_SCCR2_I2C_EN)
 342
 343
 344 #define CONFIG_CMDLINE_EDITING          1       /* command line history */
 345
 346 /* I2C */
 347 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 348 #define CONFIG_I2C_MULTI_BUS
 349
 350 /* I2C speed and slave address */
 351 #define CONFIG_SYS_I2C_SPEED            100000
 352 #define CONFIG_SYS_I2C_SLAVE            0x7F
 353
 354 /*
 355  * IIM - IC Identification Module
 356  */
 357 #undef CONFIG_FSL_IIM
 358
 359 /*
 360  * EEPROM configuration for Atmel AT24C01:
 361  * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
 362  */
 363 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 364 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x52
 365 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   30
 366 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 367
 368 /*
 369  * Ethernet configuration
 370  */
 371 #define CONFIG_MPC512x_FEC              1
 372 #define CONFIG_NET_MULTI
 373 #define CONFIG_PHY_ADDR                 0x1F
 374 #define CONFIG_MII                      1       /* MII PHY management */
 375 #define CONFIG_FEC_AN_TIMEOUT           1
 376 #define CONFIG_HAS_ETH0
 377
 378 /*
 379  * Environment
 380  */
 381 #define CONFIG_ENV_IS_IN_FLASH          1
 382 /* This has to be a multiple of the flash sector size */
 383 #define CONFIG_ENV_ADDR                 0xFFF40000
 384 #define CONFIG_ENV_SIZE                 0x2000
 385 #define CONFIG_ENV_SECT_SIZE            0x20000
 386
 387 /* Address and size of Redundant Environment Sector */
 388 #define CONFIG_ENV_ADDR_REDUND          (CONFIG_ENV_ADDR + \
 389                                          CONFIG_ENV_SECT_SIZE)
 390 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 391
 392 #define CONFIG_LOADS_ECHO               1
 393 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1
 394
 395 #include <config_cmd_default.h>
 396
 397 #define CONFIG_CMD_ASKENV
 398 #define CONFIG_CMD_DHCP
 399 #define CONFIG_CMD_EEPROM
 400 #undef CONFIG_CMD_FUSE
 401 #define CONFIG_CMD_I2C
 402 #undef CONFIG_CMD_IDE
 403 #undef CONFIG_CMD_EXT2
 404 #define CONFIG_CMD_JFFS2
 405 #define CONFIG_CMD_MII
 406 #define CONFIG_CMD_NFS
 407 #define CONFIG_CMD_PING
 408 #define CONFIG_CMD_REGINFO
 409
 410 #if defined(CONFIG_PCI)
 411 #define CONFIG_CMD_PCI
 412 #endif
 413
 414 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
 415 #define CONFIG_DOS_PARTITION
 416 #define CONFIG_MAC_PARTITION
 417 #define CONFIG_ISO_PARTITION
 418 #endif /* defined(CONFIG_CMD_IDE) */
 419
 420 /*
 421  * Miscellaneous configurable options
 422  */
 423 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 424 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 425 #define CONFIG_SYS_PROMPT       "ac14xx> "      /* Monitor Command Prompt */
 426
 427 #ifdef CONFIG_CMD_KGDB
 428 # define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
 429 #else
 430 # define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
 431 #endif
 432
 433 /* Print Buffer Size */
 434 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 435                                  sizeof(CONFIG_SYS_PROMPT) + 16)
 436 /* max number of command args */
 437 #define CONFIG_SYS_MAXARGS      32
 438 /* Boot Argument Buffer Size */
 439 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 440
 441 /*
 442  * For booting Linux, the board info and command line data
 443  * have to be in the first 8 MB of memory, since this is
 444  * the maximum mapped by the Linux kernel during initialization.
 445  */
 446 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 447
 448 /* Cache Configuration */
 449 #define CONFIG_SYS_DCACHE_SIZE          32768
 450 #define CONFIG_SYS_CACHELINE_SIZE       32
 451 #ifdef CONFIG_CMD_KGDB
 452 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of 32 */
 453 #endif
 454
 455 #define CONFIG_SYS_HID0_INIT            0x000000000
 456 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 457                                          HID0_ICE)
 458 #define CONFIG_SYS_HID2 HID2_HBE
 459
 460 #define CONFIG_HIGH_BATS                1       /* High BATs supported */
 461
 462 /*
 463  * Internal Definitions
 464  *
 465  * Boot Flags
 466  */
 467 #define BOOTFLAG_COLD                   0x01
 468 #define BOOTFLAG_WARM                   0x02
 469
 470 #ifdef CONFIG_CMD_KGDB
 471 #define CONFIG_KGDB_BAUDRATE            230400  /* speed of kgdb serial port */
 472 #endif
 473
 474 /*
 475  * Environment Configuration
 476  */
 477 #define CONFIG_ENV_OVERWRITE
 478 #define CONFIG_TIMESTAMP
 479
 480 /* default load addr for tftp and bootm */
 481 #define CONFIG_LOADADDR         400000
 482
 483 #define CONFIG_BOOTDELAY        2       /* -1 disables auto-boot */
 484
 485 /* the builtin environment and standard greeting */
 486 #define CONFIG_PREBOOT  "echo;" \
 487         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 488         "echo"
 489
 490 #define CONFIG_EXTRA_ENV_SETTINGS_DEVEL                                 \
 491         "muster_nr=-00\0"                                               \
 492         "fromram=run ramargs addip addtty; "                            \
 493                 "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "    \
 494                 "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "     \
 495                 "tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; "       \
 496                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
 497         "fromnfs=run nfsargs addip addtty; "                            \
 498                 "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "    \
 499                 "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "     \
 500                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 501         "fromflash=run nfsargs addip addtty; "                          \
 502                 "bootm fc020000 - fc000000\0"                           \
 503         "mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0"           \
 504         "recovery=run mtdargsrec addip addtty; "                        \
 505                 "bootm ffd20000 - ffee0000\0"                           \
 506         "production=run ramargs addip addtty; "                         \
 507                 "bootm fc020000 fc400000 fc000000\0"                    \
 508         "mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0"              \
 509         "prodmtd=run mtdargs addip addtty; "                            \
 510                 "bootm fc020000 - fc000000\0"                           \
 511         ""
 512
 513 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 514         "u-boot_addr_r=200000\0"                                        \
 515         "kernel_addr_r=600000\0"                                        \
 516         "fdt_addr_r=a00000\0"                                           \
 517         "ramdisk_addr_r=b00000\0"                                       \
 518         "u-boot_addr=FFF00000\0"                                        \
 519         "kernel_addr=FC020000\0"                                        \
 520         "fdt_addr=FC000000\0"                                           \
 521         "ramdisk_addr=FC400000\0"                                       \
 522         "verify=n\0"                                                    \
 523         "ramdiskfile=ac14xx/uRamdisk\0"                                 \
 524         "u-boot=ac14xx/u-boot.bin\0"                                    \
 525         "bootfile=ac14xx/uImage\0"                                      \
 526         "fdtfile=ac14xx/ac14xx.dtb\0"                                   \
 527         "netdev=eth0\0"                                                 \
 528         "consdev=ttyPSC0\0"                                             \
 529         "hostname=ac14xx\0"                                             \
 530         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 531                 "nfsroot=${serverip}:${rootpath}${muster_nr}\0" \
 532         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 533         "addip=setenv bootargs ${bootargs} "                            \
 534                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 535                 ":${hostname}:${netdev}:off panic=1\0"                  \
 536         "addtty=setenv bootargs ${bootargs} "                           \
 537                 "console=${consdev},${baudrate}\0"                      \
 538         "flash_nfs=run nfsargs addip addtty;"                           \
 539                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 540         "flash_self=run ramargs addip addtty;"                          \
 541                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 542         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 543                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 544                 "run nfsargs addip addtty;"                             \
 545                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 546         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 547                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 548                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 549                 "run ramargs addip addtty;"                             \
 550                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 551         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 552         "update=protect off ${u-boot_addr} +${filesize};"               \
 553                 "era ${u-boot_addr} +${filesize};"                      \
 554                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 555         CONFIG_EXTRA_ENV_SETTINGS_DEVEL                                 \
 556         "upd=run load update\0"                                         \
 557         ""
 558
 559 #define CONFIG_BOOTCOMMAND      "run production"
 560
 561 #define CONFIG_ARP_TIMEOUT      200UL
 562
 563 #define CONFIG_FIT              1
 564 #define CONFIG_OF_LIBFDT        1
 565 #define CONFIG_OF_BOARD_SETUP   1
 566 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 567
 568 #define OF_CPU                  "PowerPC,5121@0"
 569 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 570 #define OF_TBCLK                (bd->bi_busfreq / 4)
 571 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 572
 573 #endif  /* __CONFIG_H */