6a26269807e3a09343c206982e150889c75dfcd5
[platform/kernel/u-boot.git] / include / configs / a4m072.h
1 /*
2  * (C) Copyright 2003-2005
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * (C) Copyright 2010
6  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15  * High Level Configuration Options
16  * (easy to change)
17  */
18
19 #define CONFIG_MPC5200          1       /* This is a MPC5200 CPU */
20 #define CONFIG_A4M072           1       /* ... on A4M072 board */
21 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM */
22
23 #define CONFIG_SYS_TEXT_BASE    0xFE000000
24
25 #define CONFIG_MISC_INIT_R
26
27 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
28
29 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
30
31 /*
32  * Serial console configuration
33  */
34 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
35 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
36 /* define to enable silent console */
37 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
38
39 /*
40  * PCI Mapping:
41  * 0x40000000 - 0x4fffffff - PCI Memory
42  * 0x50000000 - 0x50ffffff - PCI IO Space
43  */
44
45 #if defined(CONFIG_PCI)
46 #define CONFIG_PCI_SCAN_SHOW    1
47 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
48
49 #define CONFIG_PCI_MEM_BUS      0x40000000
50 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
51 #define CONFIG_PCI_MEM_SIZE     0x10000000
52
53 #define CONFIG_PCI_IO_BUS       0x50000000
54 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
55 #define CONFIG_PCI_IO_SIZE      0x01000000
56 #endif
57
58 #define CONFIG_SYS_XLB_PIPELINING       1
59
60 #undef CONFIG_EEPRO100
61
62 /* USB */
63 #define CONFIG_USB_OHCI_NEW
64 #define CONFIG_SYS_OHCI_BE_CONTROLLER
65 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
66 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
67 #define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
68 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
69 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
70
71 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
72
73 /*
74  * BOOTP options
75  */
76 #define CONFIG_BOOTP_BOOTFILESIZE
77 #define CONFIG_BOOTP_BOOTPATH
78 #define CONFIG_BOOTP_GATEWAY
79 #define CONFIG_BOOTP_HOSTNAME
80
81 /*
82  * Command line configuration.
83  */
84
85 #if defined(CONFIG_PCI)
86 #define CONFIG_CMD_PCI
87 #endif
88
89 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)                /* Boot low with 32 MB Flash */
90 #define CONFIG_SYS_LOWBOOT              1
91 #define CONFIG_SYS_LOWBOOT32            1
92 #endif
93
94 /*
95  * Autobooting
96  */
97
98 #define CONFIG_SYS_AUTOLOAD     "n"
99
100 #undef  CONFIG_BOOTARGS
101 #define CONFIG_PREBOOT                          "run try_update"
102
103 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
104         "bk=run add_mtd ; run add_consolespec ; bootm 200000\0"         \
105         "cf1=diskboot 200000 0:1\0"                                     \
106         "bootcmd_cf1=run bcf1\0"                                        \
107         "bcf=setenv bootargs root=/dev/hda3\0"                          \
108         "bootcmd_nfs=run bnfs\0"                                        \
109         "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
110                 "panic=1\0"                                             \
111         "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;"                \
112                         "run norargs addip; run bk\0"                   \
113         "bnfs=nfs 200000 ${rootpath}/boot/uImage;"                      \
114                         "run nfsargs addip ; run bk\0"                  \
115         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
116                                 "nfsroot=${serverip}:${rootpath}\0"     \
117         "try_update=usb start;sleep 2;usb start;sleep 1;"               \
118                         "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;"   \
119                         "source 2F0000\0"                               \
120         "env_addr=FE060000\0"                                           \
121         "kernel_addr=FE100000\0"                                        \
122         "rootfs_addr=FE200000\0"                                        \
123         "add_mtd=setenv bootargs ${bootargs} mtdparts="                 \
124                 "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"      \
125         "bcf1=run cf1; run bcf; run addip; run bk\0"                    \
126         "add_consolespec=setenv bootargs ${bootargs} "                  \
127                                 "console=/dev/null quiet\0"             \
128         "addip=if test -n ${ethaddr};"                                  \
129                 "then if test -n ${ipaddr};"                            \
130                         "then setenv bootargs ${bootargs} "             \
131                                 "ip=${ipaddr}:${serverip}:${gatewayip}:"\
132                                 "${netmask}:${hostname}:${netdev}:off;" \
133                         "fi;"                                           \
134                 "else;"                                                 \
135                         "setenv bootargs ${bootargs} no_ethaddr;"       \
136                 "fi\0"                                                  \
137         "hostname=CPUP0\0"                                              \
138         "netdev=eth0\0"                                                 \
139         "bootcmd=run bootcmd_nor\0"                                     \
140         ""
141 /*
142  * IPB Bus clocking configuration.
143  */
144 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
145
146 /*
147  * Flash configuration
148  */
149 #define CONFIG_SYS_FLASH_BASE           0xFE000000
150 #define CONFIG_SYS_FLASH_SIZE           0x02000000
151 #if !defined(CONFIG_SYS_LOWBOOT)
152 #error "CONFIG_SYS_LOWBOOT not defined?"
153 #else   /* CONFIG_SYS_LOWBOOT */
154 #if defined(CONFIG_SYS_LOWBOOT32)
155 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
156 #endif
157 #endif  /* CONFIG_SYS_LOWBOOT */
158
159 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
160 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
161 #define CONFIG_FLASH_CFI_DRIVER
162 #define CONFIG_SYS_FLASH_CFI
163 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
164 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_CS0_START}
165 #define CONFIG_SYS_FLASH_BANKS_SIZES    {CONFIG_SYS_CS0_SIZE}
166
167 /*
168  * Environment settings
169  */
170 #define CONFIG_ENV_IS_IN_FLASH  1
171 #define CONFIG_ENV_SIZE         0x10000
172 #define CONFIG_ENV_SECT_SIZE    0x20000
173 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
174 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
175
176 #define CONFIG_ENV_OVERWRITE    1
177
178 /*
179  * Memory map
180  */
181 #define CONFIG_SYS_MBAR         0xF0000000
182 #define CONFIG_SYS_SDRAM_BASE   0x00000000
183 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
184
185 /* Use SRAM until RAM will be available */
186 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
187 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
188
189 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
190 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
191
192 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
193 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
194 #   define CONFIG_SYS_RAMBOOT           1
195 #endif
196
197 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 384 kB for Monitor   */
198 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
199 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
200
201 /*
202  * Ethernet configuration
203  */
204 #define CONFIG_MPC5xxx_FEC      1
205 #define CONFIG_MPC5xxx_FEC_MII100
206 /*
207  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
208  */
209 /* #define CONFIG_MPC5xxx_FEC_MII10 */
210 #define CONFIG_PHY_ADDR         0x1f
211 #define CONFIG_PHY_TYPE         0x79c874                /* AMD Phy Controller */
212
213 /*
214  * GPIO configuration
215  */
216 #define CONFIG_SYS_GPS_PORT_CONFIG      0x18000004
217
218 /*
219  * Miscellaneous configurable options
220  */
221 #define CONFIG_CMDLINE_EDITING  1
222 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
223 #if defined(CONFIG_CMD_KGDB)
224 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
225 #else
226 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
227 #endif
228 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
229 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
230 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
231
232 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
233 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
234
235 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
236
237 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
238 #if defined(CONFIG_CMD_KGDB)
239 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
240 #endif
241
242 /*
243  * Various low-level settings
244  */
245 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
246 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
247 /* Flash at CSBoot, CS0 */
248 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
249 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
250 #define CONFIG_SYS_BOOTCS_CFG           0x0002DD00
251 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
252 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
253 /* External SRAM at CS1 */
254 #define CONFIG_SYS_CS1_START            0x62000000
255 #define CONFIG_SYS_CS1_SIZE             0x00400000
256 #define CONFIG_SYS_CS1_CFG              0x00009930
257 #define CONFIG_SYS_SRAM_BASE            CONFIG_SYS_CS1_START
258 #define CONFIG_SYS_SRAM_SIZE            CONFIG_SYS_CS1_SIZE
259 /* LED display at CS7 */
260 #define CONFIG_SYS_CS7_START            0x6a000000
261 #define CONFIG_SYS_CS7_SIZE             (64*1024)
262 #define CONFIG_SYS_CS7_CFG              0x0000bf30
263
264 #define CONFIG_SYS_CS_BURST             0x00000000
265 #define CONFIG_SYS_CS_DEADCYCLE         0x33333003
266
267 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
268
269 /*-----------------------------------------------------------------------
270  * USB stuff
271  *-----------------------------------------------------------------------
272  */
273 #define CONFIG_USB_CLOCK        0x0001BBBB
274 #define CONFIG_USB_CONFIG       0x00001000 /* 0x4000 for SE mode */
275
276 /*-----------------------------------------------------------------------
277  * IDE/ATA stuff Supports IDE harddisk
278  *-----------------------------------------------------------------------
279  */
280
281 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
282
283 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
284 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
285
286 #define CONFIG_IDE_PREINIT
287
288 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
289 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 2 drives per IDE bus    */
290
291 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
292
293 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
294
295 /* Offset for data I/O                  */
296 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
297
298 /* Offset for normal register accesses  */
299 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
300
301 /* Offset for alternate registers       */
302 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
303
304 /* Interval between registers                                                */
305 #define CONFIG_SYS_ATA_STRIDE          4
306
307 #define CONFIG_ATAPI                   1
308
309 /*-----------------------------------------------------------------------
310  * Open firmware flat tree support
311  *-----------------------------------------------------------------------
312  */
313 #define OF_CPU                  "PowerPC,5200@0"
314 #define OF_SOC                  "soc5200@f0000000"
315 #define OF_TBCLK                (bd->bi_busfreq / 4)
316 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
317
318 /* Support for the 7-segment display */
319 #define CONFIG_SYS_DISP_CHR_RAM      CONFIG_SYS_CS7_START
320 #define CONFIG_SHOW_ACTIVITY            /* used for display realization */
321
322 #define CONFIG_SHOW_BOOT_PROGRESS
323
324 #endif /* __CONFIG_H */