2 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 * High Level Configuration Options
15 #define CONFIG_MPC5200
16 #define CONFIG_A3M071 /* A3M071 board */
18 #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
20 #define CONFIG_SPL_TARGET "u-boot-img.bin"
22 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
24 #define CONFIG_MISC_INIT_R
25 #define CONFIG_SYS_LOWBOOT /* Enable lowboot */
28 #define CONFIG_HOSTNAME a4m2k
30 #define CONFIG_HOSTNAME a3m071
33 #define CONFIG_BOOTCOUNT_LIMIT
36 * Serial console configuration
38 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
39 #define CONFIG_SYS_BAUDRATE_TABLE \
40 { 9600, 19200, 38400, 57600, 115200, 230400 }
43 * Command line configuration.
45 #define CONFIG_CMD_BSP
46 #define CONFIG_CMD_REGINFO
47 #define CONFIG_BOOTP_SEND_HOSTNAME
48 #define CONFIG_BOOTP_SERVERIP
49 #define CONFIG_BOOTP_MAY_FAIL
50 #define CONFIG_BOOTP_BOOTPATH
51 #define CONFIG_BOOTP_GATEWAY
52 #define CONFIG_BOOTP_SERVERIP
53 #define CONFIG_NET_RETRY_COUNT 3
54 #define CONFIG_NETCONSOLE
55 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
56 #define CONFIG_MTD_PARTITIONS /* needed for UBI */
57 #define CONFIG_FLASH_CFI_MTD
58 #define MTDIDS_DEFAULT "nor0=fc000000.flash"
59 #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
72 #define CONFIG_LZO /* needed for UBI */
73 #define CONFIG_RBTREE /* needed for UBI */
74 #define CONFIG_CMD_MTDPARTS
75 #define CONFIG_CMD_UBIFS
78 * IPB Bus clocking configuration.
80 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
81 /* define for 66MHz speed - undef for 33MHz PCI clock speed */
83 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
85 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
88 /* maximum size of the flat tree (8K) */
89 #define OF_FLAT_TREE_MAX_SIZE 8192
91 #define OF_CPU "PowerPC,5200@0"
92 #define OF_SOC "soc5200@f0000000"
93 #define OF_TBCLK (bd->bi_busfreq / 4)
94 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
97 * NOR flash configuration
99 #define CONFIG_SYS_FLASH_BASE 0xfc000000
100 #define CONFIG_SYS_FLASH_SIZE 0x02000000
101 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
103 #define CONFIG_SYS_MAX_FLASH_BANKS 1
104 #define CONFIG_SYS_MAX_FLASH_SECT 256
105 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
106 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
107 #define CONFIG_SYS_FLASH_LOCK_TOUT 5
108 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
109 #define CONFIG_SYS_FLASH_PROTECTION
110 #define CONFIG_FLASH_CFI_DRIVER
111 #define CONFIG_SYS_FLASH_CFI
112 #define CONFIG_SYS_FLASH_EMPTY_INFO
113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
114 #define CONFIG_FLASH_VERIFY
117 * Environment settings
119 #define CONFIG_ENV_IS_IN_FLASH
120 #define CONFIG_ENV_SIZE 0x10000
121 #define CONFIG_ENV_SECT_SIZE 0x20000
122 #define CONFIG_ENV_OVERWRITE
123 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
124 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
129 #define CONFIG_SYS_MBAR 0xf0000000
130 #define CONFIG_SYS_SDRAM_BASE 0x00000000
131 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
133 /* Use SRAM until RAM will be available */
134 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
135 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
137 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
138 GENERATED_GBL_DATA_SIZE)
139 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
143 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
144 #define CONFIG_SYS_MALLOC_LEN (4 << 20)
145 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
148 * Ethernet configuration
150 #define CONFIG_MPC5xxx_FEC
151 #define CONFIG_MPC5xxx_FEC_MII100
153 #define CONFIG_PHY_ADDR 0x01
155 #define CONFIG_PHY_ADDR 0x00
163 * GPIO-config depends on failsave-level
164 * failsave 0 means just MPX-config, no digiboard, no fpga
165 * 1 means digiboard ok
170 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
172 /* for failsave-level 0 - full failsave */
173 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
174 /* for failsave-level 1 - only digiboard ok */
175 #define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
176 /* for failsave-level 2 - all ok */
177 #define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
180 #define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
181 #if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
182 #define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
186 * Configuration matrix
188 * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
189 * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
190 * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
191 * || ||| || | ||| | | | |
192 * || ||| || | ||| | | | | bit rev name
193 * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
194 * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
195 * ||| || | ||| | | | | 2 29 ALTs
196 * +++-++--+---+++-+---+---+---+- 3 28 ALTs
197 * ++-++--+---+++-+---+---+---+- 4 27 CS7
198 * +-++--+---+++-+---+---+---+- 5 26 CS6
199 * || | ||| | | | | 6 25 ATA
200 * ++--+---+++-+---+---+---+- 7 24 ATA
201 * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
202 * | ||| | | | | 9 22 IRDA
203 * | ||| | | | | 10 21 IRDA
204 * +---+++-+---+---+---+- 11 20 IRDA
205 * ||| | | | | 12 19 Ether
206 * ||| | | | | 13 18 Ether
207 * ||| | | | | 14 17 Ether
208 * +++-+---+---+---+- 15 16 Ether
209 * ++-+---+---+---+- 16 15 PCI_DIS
210 * +-+---+---+---+- 17 14 USB_SE
212 * +---+---+---+- 19 12 USB
216 * +---+---+- 23 8 PSC3
228 * Miscellaneous configurable options
230 #define CONFIG_SYS_LONGHELP
232 #define CONFIG_CMDLINE_EDITING
234 #if defined(CONFIG_CMD_KGDB)
235 #define CONFIG_SYS_CBSIZE 1024
237 #define CONFIG_SYS_CBSIZE 256
239 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
240 #define CONFIG_SYS_MAXARGS 16
241 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
243 #define CONFIG_SYS_MEMTEST_START 0x00100000
244 #define CONFIG_SYS_MEMTEST_END 0x00f00000
246 #define CONFIG_SYS_LOAD_ADDR 0x00100000
249 * Various low-level settings
251 #define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
252 #define CONFIG_SYS_HID0_FINAL HID0_ICE
254 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
255 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
256 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
257 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
261 #define CONFIG_SYS_CS1_START 0xf1000000
262 #define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
265 #define CONFIG_SYS_CS2_START 0xe0000000
266 #define CONFIG_SYS_CS2_SIZE 0x00100000
268 /* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
269 #define CONFIG_SYS_CS3_START 0xE9000000
271 #define CONFIG_SYS_CS3_SIZE 0x00100000
273 #define CONFIG_SYS_CS3_SIZE 0x00080000
275 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
276 #define CONFIG_SYS_CS3_CFG 0x0032B900
279 /* Diagnosis Interface - see ticket #63 */
280 #define CONFIG_SYS_CS4_START 0xEA000000
281 #define CONFIG_SYS_CS4_SIZE 0x00000001
282 /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
283 #define CONFIG_SYS_CS4_CFG 0x0002B900
286 /* FPGA master io (64kiB / 1MiB) - see ticket #66 */
287 #define CONFIG_SYS_CS5_START 0xE8000000
289 #define CONFIG_SYS_CS5_SIZE 0x00100000
291 #define CONFIG_SYS_CS5_SIZE 0x00010000
293 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
294 #define CONFIG_SYS_CS5_CFG 0x0032B900
296 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
297 #define CONFIG_SYS_BOOTCS_CFG 0x0006F900
298 #define CONFIG_SYS_CS1_CFG 0x0008FD00
299 #define CONFIG_SYS_CS2_CFG 0x0006F90C
300 #else /* for pci_clk = 33 MHz */
301 #define CONFIG_SYS_BOOTCS_CFG 0x0002F900
302 #define CONFIG_SYS_CS1_CFG 0x0001FB00
303 #define CONFIG_SYS_CS2_CFG 0x0002F90C
306 #define CONFIG_SYS_CS_BURST 0x00000000
307 /* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
308 /* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
309 /* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
310 #define CONFIG_SYS_CS_DEADCYCLE 0x33030000
312 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
315 * Environment Configuration
318 #undef CONFIG_BOOTARGS
320 #define CONFIG_SYS_AUTOLOAD "n"
322 #define CONFIG_PREBOOT "echo;" \
323 "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
324 "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
327 #undef CONFIG_BOOTARGS
329 #define CONFIG_SYS_FDT_BASE 0xfc1e0000
330 #define CONFIG_SYS_FDT_SIZE (16<<10)
332 #define CONFIG_EXTRA_ENV_SETTINGS \
335 "loadaddr=200000\0" \
336 "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
337 "kernel_addr_r=1000000\0" \
338 "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
339 "fdt_addr_r=1800000\0" \
340 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
341 "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
342 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
343 "rootpath=/opt/eldk-5.2.1/powerpc/" \
344 "core-image-minimal-mtdutils-dropbear-generic\0" \
345 "consoledev=ttyPSC0\0" \
346 "nfsargs=setenv bootargs root=/dev/nfs rw " \
347 "nfsroot=${serverip}:${rootpath}\0" \
348 "ramargs=setenv bootargs root=/dev/ram rw\0" \
349 "mtdargs=setenv bootargs root=/dev/mtdblock8 " \
350 "rootfstype=squashfs,jffs2\0" \
351 "addhost=setenv bootargs ${bootargs} " \
352 "hostname=${hostname}\0" \
353 "addip=setenv bootargs ${bootargs} " \
354 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
355 ":${hostname}:${netdev}:off panic=1\0" \
356 "addtty=setenv bootargs ${bootargs} " \
357 "console=${consoledev},${baudrate}\0" \
358 "flash_nfs=run nfsargs addip addtty addmtd addhost;" \
359 "bootm ${kernel_addr} - ${fdt_addr}\0" \
360 "flash_mtd=run mtdargs addip addtty addmtd addhost;" \
361 "bootm ${kernel_addr} - ${fdt_addr}\0" \
362 "flash_self=run ramargs addip addtty addmtd addhost;" \
363 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
364 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
365 "tftp ${fdt_addr_r} ${fdtfile};" \
366 "run nfsargs addip addtty addmtd addhost;" \
367 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
368 "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
369 "/u-boot-img.bin\0" \
370 "update=protect off fc000000 fc07ffff;" \
371 "era fc000000 fc07ffff;" \
372 "cp.b ${loadaddr} fc000000 ${filesize}\0" \
373 "upd=run load;run update\0" \
374 "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
375 "run mtdargs addip addtty addmtd addhost;" \
376 "fdt addr 1800000;fdt boardsetup;fdt chosen;" \
377 "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
378 "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
379 "erase fc200000 fc6fffff;" \
380 "cp.b 1000000 fc200000 ${filesize}" \
381 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
382 "mtdids=" MTDIDS_DEFAULT "\0" \
383 "mtdparts=" MTDPARTS_DEFAULT "\0" \
386 #define CONFIG_BOOTCOMMAND "run flash_mtd"
389 * SPL related defines
391 #define CONFIG_SPL_FRAMEWORK
392 #define CONFIG_SPL_BOARD_INIT
393 #define CONFIG_SPL_TEXT_BASE 0xfc000000
395 /* Place BSS for SPL near end of SDRAM */
396 #define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
397 #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
399 /* Place patched DT blob (fdt) at this address */
400 #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
402 /* Settings for real U-Boot to be loaded from NOR flash */
404 extern char __spl_flash_end[];
406 #define CONFIG_SYS_UBOOT_BASE __spl_flash_end
407 #define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
408 #define CONFIG_SYS_UBOOT_START 0x1000100
410 #endif /* __CONFIG_H */