2 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 * High Level Configuration Options
15 #define CONFIG_MPC5200
16 #define CONFIG_A3M071 /* A3M071 board */
17 #define CONFIG_DISPLAY_BOARDINFO
19 #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
21 #define CONFIG_SPL_TARGET "u-boot-img.bin"
23 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
25 #define CONFIG_MISC_INIT_R
26 #define CONFIG_SYS_LOWBOOT /* Enable lowboot */
29 #define CONFIG_HOSTNAME a4m2k
31 #define CONFIG_HOSTNAME a3m071
34 #define CONFIG_BOOTCOUNT_LIMIT
37 * Serial console configuration
39 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
40 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
41 #define CONFIG_SYS_BAUDRATE_TABLE \
42 { 9600, 19200, 38400, 57600, 115200, 230400 }
45 * Command line configuration.
47 #define CONFIG_CMD_BSP
48 #define CONFIG_CMD_CACHE
49 #define CONFIG_CMD_MII
50 #define CONFIG_CMD_REGINFO
51 #define CONFIG_CMD_DHCP
52 #define CONFIG_BOOTP_SEND_HOSTNAME
53 #define CONFIG_BOOTP_SERVERIP
54 #define CONFIG_BOOTP_MAY_FAIL
55 #define CONFIG_BOOTP_BOOTPATH
56 #define CONFIG_BOOTP_GATEWAY
57 #define CONFIG_BOOTP_SERVERIP
58 #define CONFIG_NET_RETRY_COUNT 3
59 #define CONFIG_CMD_LINK_LOCAL
60 #define CONFIG_NETCONSOLE
61 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
62 #define CONFIG_CMD_PING
63 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
64 #define CONFIG_MTD_PARTITIONS /* needed for UBI */
65 #define CONFIG_FLASH_CFI_MTD
66 #define MTDIDS_DEFAULT "nor0=fc000000.flash"
67 #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
80 #define CONFIG_LZO /* needed for UBI */
81 #define CONFIG_RBTREE /* needed for UBI */
82 #define CONFIG_CMD_MTDPARTS
83 #define CONFIG_CMD_UBI
84 #define CONFIG_CMD_UBIFS
88 * IPB Bus clocking configuration.
90 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
91 /* define for 66MHz speed - undef for 33MHz PCI clock speed */
93 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
95 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
98 /* pass open firmware flat tree */
99 #define CONFIG_OF_LIBFDT
100 #define CONFIG_OF_BOARD_SETUP
102 /* maximum size of the flat tree (8K) */
103 #define OF_FLAT_TREE_MAX_SIZE 8192
105 #define OF_CPU "PowerPC,5200@0"
106 #define OF_SOC "soc5200@f0000000"
107 #define OF_TBCLK (bd->bi_busfreq / 4)
108 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
111 * NOR flash configuration
113 #define CONFIG_SYS_FLASH_BASE 0xfc000000
114 #define CONFIG_SYS_FLASH_SIZE 0x02000000
115 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
117 #define CONFIG_SYS_MAX_FLASH_BANKS 1
118 #define CONFIG_SYS_MAX_FLASH_SECT 256
119 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
120 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
121 #define CONFIG_SYS_FLASH_LOCK_TOUT 5
122 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
123 #define CONFIG_SYS_FLASH_PROTECTION
124 #define CONFIG_FLASH_CFI_DRIVER
125 #define CONFIG_SYS_FLASH_CFI
126 #define CONFIG_SYS_FLASH_EMPTY_INFO
127 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
128 #define CONFIG_FLASH_VERIFY
131 * Environment settings
133 #define CONFIG_ENV_IS_IN_FLASH
134 #define CONFIG_ENV_SIZE 0x10000
135 #define CONFIG_ENV_SECT_SIZE 0x20000
136 #define CONFIG_ENV_OVERWRITE
137 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
138 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
143 #define CONFIG_SYS_MBAR 0xf0000000
144 #define CONFIG_SYS_SDRAM_BASE 0x00000000
145 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
147 /* Use SRAM until RAM will be available */
148 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
149 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
151 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
152 GENERATED_GBL_DATA_SIZE)
153 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
157 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
158 #define CONFIG_SYS_MALLOC_LEN (4 << 20)
159 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
162 * Ethernet configuration
164 #define CONFIG_MPC5xxx_FEC
165 #define CONFIG_MPC5xxx_FEC_MII100
167 #define CONFIG_PHY_ADDR 0x01
169 #define CONFIG_PHY_ADDR 0x00
177 * GPIO-config depends on failsave-level
178 * failsave 0 means just MPX-config, no digiboard, no fpga
179 * 1 means digiboard ok
184 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
186 /* for failsave-level 0 - full failsave */
187 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
188 /* for failsave-level 1 - only digiboard ok */
189 #define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
190 /* for failsave-level 2 - all ok */
191 #define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
194 #define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
195 #if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
196 #define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
200 * Configuration matrix
202 * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
203 * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
204 * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
205 * || ||| || | ||| | | | |
206 * || ||| || | ||| | | | | bit rev name
207 * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
208 * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
209 * ||| || | ||| | | | | 2 29 ALTs
210 * +++-++--+---+++-+---+---+---+- 3 28 ALTs
211 * ++-++--+---+++-+---+---+---+- 4 27 CS7
212 * +-++--+---+++-+---+---+---+- 5 26 CS6
213 * || | ||| | | | | 6 25 ATA
214 * ++--+---+++-+---+---+---+- 7 24 ATA
215 * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
216 * | ||| | | | | 9 22 IRDA
217 * | ||| | | | | 10 21 IRDA
218 * +---+++-+---+---+---+- 11 20 IRDA
219 * ||| | | | | 12 19 Ether
220 * ||| | | | | 13 18 Ether
221 * ||| | | | | 14 17 Ether
222 * +++-+---+---+---+- 15 16 Ether
223 * ++-+---+---+---+- 16 15 PCI_DIS
224 * +-+---+---+---+- 17 14 USB_SE
226 * +---+---+---+- 19 12 USB
230 * +---+---+- 23 8 PSC3
243 * Miscellaneous configurable options
245 #define CONFIG_SYS_LONGHELP
247 #define CONFIG_CMDLINE_EDITING
248 #define CONFIG_SYS_HUSH_PARSER
249 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
251 #if defined(CONFIG_CMD_KGDB)
252 #define CONFIG_SYS_CBSIZE 1024
254 #define CONFIG_SYS_CBSIZE 256
256 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
257 #define CONFIG_SYS_MAXARGS 16
258 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
260 #define CONFIG_SYS_MEMTEST_START 0x00100000
261 #define CONFIG_SYS_MEMTEST_END 0x00f00000
263 #define CONFIG_SYS_LOAD_ADDR 0x00100000
266 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
269 * Various low-level settings
271 #define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
272 #define CONFIG_SYS_HID0_FINAL HID0_ICE
274 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
275 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
276 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
277 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
281 #define CONFIG_SYS_CS1_START 0xf1000000
282 #define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
285 #define CONFIG_SYS_CS2_START 0xe0000000
286 #define CONFIG_SYS_CS2_SIZE 0x00100000
288 /* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
289 #define CONFIG_SYS_CS3_START 0xE9000000
291 #define CONFIG_SYS_CS3_SIZE 0x00100000
293 #define CONFIG_SYS_CS3_SIZE 0x00080000
295 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
296 #define CONFIG_SYS_CS3_CFG 0x0032B900
299 /* Diagnosis Interface - see ticket #63 */
300 #define CONFIG_SYS_CS4_START 0xEA000000
301 #define CONFIG_SYS_CS4_SIZE 0x00000001
302 /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
303 #define CONFIG_SYS_CS4_CFG 0x0002B900
306 /* FPGA master io (64kiB / 1MiB) - see ticket #66 */
307 #define CONFIG_SYS_CS5_START 0xE8000000
309 #define CONFIG_SYS_CS5_SIZE 0x00100000
311 #define CONFIG_SYS_CS5_SIZE 0x00010000
313 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
314 #define CONFIG_SYS_CS5_CFG 0x0032B900
316 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
317 #define CONFIG_SYS_BOOTCS_CFG 0x0006F900
318 #define CONFIG_SYS_CS1_CFG 0x0008FD00
319 #define CONFIG_SYS_CS2_CFG 0x0006F90C
320 #else /* for pci_clk = 33 MHz */
321 #define CONFIG_SYS_BOOTCS_CFG 0x0002F900
322 #define CONFIG_SYS_CS1_CFG 0x0001FB00
323 #define CONFIG_SYS_CS2_CFG 0x0002F90C
326 #define CONFIG_SYS_CS_BURST 0x00000000
327 /* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
328 /* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
329 /* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
330 #define CONFIG_SYS_CS_DEADCYCLE 0x33030000
332 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
335 * Environment Configuration
338 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
339 #undef CONFIG_BOOTARGS
340 #define CONFIG_ZERO_BOOTDELAY_CHECK
342 #define CONFIG_SYS_AUTOLOAD "n"
344 #define CONFIG_PREBOOT "echo;" \
345 "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
346 "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
349 #undef CONFIG_BOOTARGS
351 #define CONFIG_SYS_OS_BASE 0xfc200000
352 #define CONFIG_SYS_FDT_BASE 0xfc1e0000
354 #define CONFIG_EXTRA_ENV_SETTINGS \
357 "loadaddr=200000\0" \
358 "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
359 "kernel_addr_r=1000000\0" \
360 "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
361 "fdt_addr_r=1800000\0" \
362 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
363 "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
364 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
365 "rootpath=/opt/eldk-5.2.1/powerpc/" \
366 "core-image-minimal-mtdutils-dropbear-generic\0" \
367 "consoledev=ttyPSC0\0" \
368 "nfsargs=setenv bootargs root=/dev/nfs rw " \
369 "nfsroot=${serverip}:${rootpath}\0" \
370 "ramargs=setenv bootargs root=/dev/ram rw\0" \
371 "mtdargs=setenv bootargs root=/dev/mtdblock8 " \
372 "rootfstype=squashfs,jffs2\0" \
373 "addhost=setenv bootargs ${bootargs} " \
374 "hostname=${hostname}\0" \
375 "addip=setenv bootargs ${bootargs} " \
376 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
377 ":${hostname}:${netdev}:off panic=1\0" \
378 "addtty=setenv bootargs ${bootargs} " \
379 "console=${consoledev},${baudrate}\0" \
380 "flash_nfs=run nfsargs addip addtty addmtd addhost;" \
381 "bootm ${kernel_addr} - ${fdt_addr}\0" \
382 "flash_mtd=run mtdargs addip addtty addmtd addhost;" \
383 "bootm ${kernel_addr} - ${fdt_addr}\0" \
384 "flash_self=run ramargs addip addtty addmtd addhost;" \
385 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
386 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
387 "tftp ${fdt_addr_r} ${fdtfile};" \
388 "run nfsargs addip addtty addmtd addhost;" \
389 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
390 "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
391 "/u-boot-img.bin\0" \
392 "update=protect off fc000000 fc07ffff;" \
393 "era fc000000 fc07ffff;" \
394 "cp.b ${loadaddr} fc000000 ${filesize}\0" \
395 "upd=run load;run update\0" \
396 "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
397 "run mtdargs addip addtty addmtd addhost;" \
398 "fdt addr 1800000;fdt boardsetup;fdt chosen;" \
399 "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
400 "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
401 "erase fc200000 fc6fffff;" \
402 "cp.b 1000000 fc200000 ${filesize}" \
403 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
404 "mtdids=" MTDIDS_DEFAULT "\0" \
405 "mtdparts=" MTDPARTS_DEFAULT "\0" \
408 #define CONFIG_BOOTCOMMAND "run flash_mtd"
411 * SPL related defines
413 #define CONFIG_SPL_FRAMEWORK
414 #define CONFIG_SPL_BOARD_INIT
415 #define CONFIG_SPL_NOR_SUPPORT
416 #define CONFIG_SPL_TEXT_BASE 0xfc000000
417 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
418 #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
419 #define CONFIG_SPL_SERIAL_SUPPORT
421 /* Place BSS for SPL near end of SDRAM */
422 #define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
423 #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
425 #define CONFIG_SPL_OS_BOOT
426 #define CONFIG_SPL_ENV_SUPPORT
427 /* Place patched DT blob (fdt) at this address */
428 #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
430 /* Settings for real U-Boot to be loaded from NOR flash */
432 extern char __spl_flash_end[];
434 #define CONFIG_SYS_UBOOT_BASE __spl_flash_end
435 #define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
436 #define CONFIG_SYS_UBOOT_START 0x1000100
438 #endif /* __CONFIG_H */