2 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 * High Level Configuration Options
15 #define CONFIG_MPC5200
16 #define CONFIG_A3M071 /* A3M071 board */
18 #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
20 #define CONFIG_SPL_TARGET "u-boot-img.bin"
22 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
24 #define CONFIG_MISC_INIT_R
25 #define CONFIG_SYS_LOWBOOT /* Enable lowboot */
28 #define CONFIG_HOSTNAME a4m2k
30 #define CONFIG_HOSTNAME a3m071
33 #define CONFIG_BOOTCOUNT_LIMIT
36 * Serial console configuration
38 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
39 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
40 #define CONFIG_SYS_BAUDRATE_TABLE \
41 { 9600, 19200, 38400, 57600, 115200, 230400 }
44 * Command line configuration.
46 #define CONFIG_CMD_BSP
47 #define CONFIG_CMD_REGINFO
48 #define CONFIG_BOOTP_SEND_HOSTNAME
49 #define CONFIG_BOOTP_SERVERIP
50 #define CONFIG_BOOTP_MAY_FAIL
51 #define CONFIG_BOOTP_BOOTPATH
52 #define CONFIG_BOOTP_GATEWAY
53 #define CONFIG_BOOTP_SERVERIP
54 #define CONFIG_NET_RETRY_COUNT 3
55 #define CONFIG_NETCONSOLE
56 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
57 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
58 #define CONFIG_MTD_PARTITIONS /* needed for UBI */
59 #define CONFIG_FLASH_CFI_MTD
60 #define MTDIDS_DEFAULT "nor0=fc000000.flash"
61 #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
74 #define CONFIG_LZO /* needed for UBI */
75 #define CONFIG_RBTREE /* needed for UBI */
76 #define CONFIG_CMD_MTDPARTS
77 #define CONFIG_CMD_UBIFS
80 * IPB Bus clocking configuration.
82 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
83 /* define for 66MHz speed - undef for 33MHz PCI clock speed */
85 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
87 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
90 /* maximum size of the flat tree (8K) */
91 #define OF_FLAT_TREE_MAX_SIZE 8192
93 #define OF_CPU "PowerPC,5200@0"
94 #define OF_SOC "soc5200@f0000000"
95 #define OF_TBCLK (bd->bi_busfreq / 4)
96 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
99 * NOR flash configuration
101 #define CONFIG_SYS_FLASH_BASE 0xfc000000
102 #define CONFIG_SYS_FLASH_SIZE 0x02000000
103 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
105 #define CONFIG_SYS_MAX_FLASH_BANKS 1
106 #define CONFIG_SYS_MAX_FLASH_SECT 256
107 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
108 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
109 #define CONFIG_SYS_FLASH_LOCK_TOUT 5
110 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
111 #define CONFIG_SYS_FLASH_PROTECTION
112 #define CONFIG_FLASH_CFI_DRIVER
113 #define CONFIG_SYS_FLASH_CFI
114 #define CONFIG_SYS_FLASH_EMPTY_INFO
115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
116 #define CONFIG_FLASH_VERIFY
119 * Environment settings
121 #define CONFIG_ENV_IS_IN_FLASH
122 #define CONFIG_ENV_SIZE 0x10000
123 #define CONFIG_ENV_SECT_SIZE 0x20000
124 #define CONFIG_ENV_OVERWRITE
125 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
126 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
131 #define CONFIG_SYS_MBAR 0xf0000000
132 #define CONFIG_SYS_SDRAM_BASE 0x00000000
133 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
135 /* Use SRAM until RAM will be available */
136 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
137 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
139 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
140 GENERATED_GBL_DATA_SIZE)
141 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
143 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
145 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
146 #define CONFIG_SYS_MALLOC_LEN (4 << 20)
147 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
150 * Ethernet configuration
152 #define CONFIG_MPC5xxx_FEC
153 #define CONFIG_MPC5xxx_FEC_MII100
155 #define CONFIG_PHY_ADDR 0x01
157 #define CONFIG_PHY_ADDR 0x00
165 * GPIO-config depends on failsave-level
166 * failsave 0 means just MPX-config, no digiboard, no fpga
167 * 1 means digiboard ok
172 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
174 /* for failsave-level 0 - full failsave */
175 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
176 /* for failsave-level 1 - only digiboard ok */
177 #define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
178 /* for failsave-level 2 - all ok */
179 #define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
182 #define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
183 #if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
184 #define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
188 * Configuration matrix
190 * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
191 * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
192 * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
193 * || ||| || | ||| | | | |
194 * || ||| || | ||| | | | | bit rev name
195 * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
196 * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
197 * ||| || | ||| | | | | 2 29 ALTs
198 * +++-++--+---+++-+---+---+---+- 3 28 ALTs
199 * ++-++--+---+++-+---+---+---+- 4 27 CS7
200 * +-++--+---+++-+---+---+---+- 5 26 CS6
201 * || | ||| | | | | 6 25 ATA
202 * ++--+---+++-+---+---+---+- 7 24 ATA
203 * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
204 * | ||| | | | | 9 22 IRDA
205 * | ||| | | | | 10 21 IRDA
206 * +---+++-+---+---+---+- 11 20 IRDA
207 * ||| | | | | 12 19 Ether
208 * ||| | | | | 13 18 Ether
209 * ||| | | | | 14 17 Ether
210 * +++-+---+---+---+- 15 16 Ether
211 * ++-+---+---+---+- 16 15 PCI_DIS
212 * +-+---+---+---+- 17 14 USB_SE
214 * +---+---+---+- 19 12 USB
218 * +---+---+- 23 8 PSC3
230 * Miscellaneous configurable options
232 #define CONFIG_SYS_LONGHELP
234 #define CONFIG_CMDLINE_EDITING
236 #if defined(CONFIG_CMD_KGDB)
237 #define CONFIG_SYS_CBSIZE 1024
239 #define CONFIG_SYS_CBSIZE 256
241 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
242 #define CONFIG_SYS_MAXARGS 16
243 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
245 #define CONFIG_SYS_MEMTEST_START 0x00100000
246 #define CONFIG_SYS_MEMTEST_END 0x00f00000
248 #define CONFIG_SYS_LOAD_ADDR 0x00100000
250 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
253 * Various low-level settings
255 #define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
256 #define CONFIG_SYS_HID0_FINAL HID0_ICE
258 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
259 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
260 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
261 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
265 #define CONFIG_SYS_CS1_START 0xf1000000
266 #define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
269 #define CONFIG_SYS_CS2_START 0xe0000000
270 #define CONFIG_SYS_CS2_SIZE 0x00100000
272 /* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
273 #define CONFIG_SYS_CS3_START 0xE9000000
275 #define CONFIG_SYS_CS3_SIZE 0x00100000
277 #define CONFIG_SYS_CS3_SIZE 0x00080000
279 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
280 #define CONFIG_SYS_CS3_CFG 0x0032B900
283 /* Diagnosis Interface - see ticket #63 */
284 #define CONFIG_SYS_CS4_START 0xEA000000
285 #define CONFIG_SYS_CS4_SIZE 0x00000001
286 /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
287 #define CONFIG_SYS_CS4_CFG 0x0002B900
290 /* FPGA master io (64kiB / 1MiB) - see ticket #66 */
291 #define CONFIG_SYS_CS5_START 0xE8000000
293 #define CONFIG_SYS_CS5_SIZE 0x00100000
295 #define CONFIG_SYS_CS5_SIZE 0x00010000
297 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
298 #define CONFIG_SYS_CS5_CFG 0x0032B900
300 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
301 #define CONFIG_SYS_BOOTCS_CFG 0x0006F900
302 #define CONFIG_SYS_CS1_CFG 0x0008FD00
303 #define CONFIG_SYS_CS2_CFG 0x0006F90C
304 #else /* for pci_clk = 33 MHz */
305 #define CONFIG_SYS_BOOTCS_CFG 0x0002F900
306 #define CONFIG_SYS_CS1_CFG 0x0001FB00
307 #define CONFIG_SYS_CS2_CFG 0x0002F90C
310 #define CONFIG_SYS_CS_BURST 0x00000000
311 /* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
312 /* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
313 /* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
314 #define CONFIG_SYS_CS_DEADCYCLE 0x33030000
316 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
319 * Environment Configuration
322 #undef CONFIG_BOOTARGS
324 #define CONFIG_SYS_AUTOLOAD "n"
326 #define CONFIG_PREBOOT "echo;" \
327 "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
328 "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
331 #undef CONFIG_BOOTARGS
333 #define CONFIG_SYS_OS_BASE 0xfc200000
334 #define CONFIG_SYS_FDT_BASE 0xfc1e0000
335 #define CONFIG_SYS_FDT_SIZE (16<<10)
337 #define CONFIG_EXTRA_ENV_SETTINGS \
340 "loadaddr=200000\0" \
341 "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
342 "kernel_addr_r=1000000\0" \
343 "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
344 "fdt_addr_r=1800000\0" \
345 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
346 "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
347 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
348 "rootpath=/opt/eldk-5.2.1/powerpc/" \
349 "core-image-minimal-mtdutils-dropbear-generic\0" \
350 "consoledev=ttyPSC0\0" \
351 "nfsargs=setenv bootargs root=/dev/nfs rw " \
352 "nfsroot=${serverip}:${rootpath}\0" \
353 "ramargs=setenv bootargs root=/dev/ram rw\0" \
354 "mtdargs=setenv bootargs root=/dev/mtdblock8 " \
355 "rootfstype=squashfs,jffs2\0" \
356 "addhost=setenv bootargs ${bootargs} " \
357 "hostname=${hostname}\0" \
358 "addip=setenv bootargs ${bootargs} " \
359 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
360 ":${hostname}:${netdev}:off panic=1\0" \
361 "addtty=setenv bootargs ${bootargs} " \
362 "console=${consoledev},${baudrate}\0" \
363 "flash_nfs=run nfsargs addip addtty addmtd addhost;" \
364 "bootm ${kernel_addr} - ${fdt_addr}\0" \
365 "flash_mtd=run mtdargs addip addtty addmtd addhost;" \
366 "bootm ${kernel_addr} - ${fdt_addr}\0" \
367 "flash_self=run ramargs addip addtty addmtd addhost;" \
368 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
369 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
370 "tftp ${fdt_addr_r} ${fdtfile};" \
371 "run nfsargs addip addtty addmtd addhost;" \
372 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
373 "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
374 "/u-boot-img.bin\0" \
375 "update=protect off fc000000 fc07ffff;" \
376 "era fc000000 fc07ffff;" \
377 "cp.b ${loadaddr} fc000000 ${filesize}\0" \
378 "upd=run load;run update\0" \
379 "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
380 "run mtdargs addip addtty addmtd addhost;" \
381 "fdt addr 1800000;fdt boardsetup;fdt chosen;" \
382 "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
383 "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
384 "erase fc200000 fc6fffff;" \
385 "cp.b 1000000 fc200000 ${filesize}" \
386 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
387 "mtdids=" MTDIDS_DEFAULT "\0" \
388 "mtdparts=" MTDPARTS_DEFAULT "\0" \
391 #define CONFIG_BOOTCOMMAND "run flash_mtd"
394 * SPL related defines
396 #define CONFIG_SPL_FRAMEWORK
397 #define CONFIG_SPL_BOARD_INIT
398 #define CONFIG_SPL_TEXT_BASE 0xfc000000
400 /* Place BSS for SPL near end of SDRAM */
401 #define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
402 #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
404 #define CONFIG_SPL_OS_BOOT
405 /* Place patched DT blob (fdt) at this address */
406 #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
408 /* Settings for real U-Boot to be loaded from NOR flash */
410 extern char __spl_flash_end[];
412 #define CONFIG_SYS_UBOOT_BASE __spl_flash_end
413 #define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
414 #define CONFIG_SYS_UBOOT_START 0x1000100
416 #endif /* __CONFIG_H */