2 * (C) Copyright 2009 Faraday Technology
3 * Po-Yu Chuang <ratbert@faraday-tech.com>
5 * Configuation settings for the Faraday A320 board.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/a320.h>
16 * mach-type definition
18 #define MACH_TYPE_FARADAY 758
19 #define CONFIG_MACH_TYPE MACH_TYPE_FARADAY
22 * Linux kernel tagged list
24 #define CONFIG_CMDLINE_TAG
25 #define CONFIG_SETUP_MEMORY_TAGS
28 * CPU and Board Configuration Options
30 #undef CONFIG_SKIP_LOWLEVEL_INIT
33 * Power Management Unit
35 #define CONFIG_FTPMU010_POWER
40 #define CONFIG_SYS_HZ 1000 /* timer ticks per second */
45 #define CONFIG_RTC_FTRTC010
48 * Serial console configuration
51 /* FTUART is a high speed NS 16C550A compatible UART */
52 #define CONFIG_BAUDRATE 38400
53 #define CONFIG_CONS_INDEX 1
54 #define CONFIG_SYS_NS16550
55 #define CONFIG_SYS_NS16550_SERIAL
56 #define CONFIG_SYS_NS16550_COM1 0x98200000
57 #define CONFIG_SYS_NS16550_REG_SIZE -4
58 #define CONFIG_SYS_NS16550_CLK 18432000
63 #define CONFIG_FTMAC100
65 #define CONFIG_BOOTDELAY 3
68 * Command line configuration.
70 #include <config_cmd_default.h>
72 #define CONFIG_CMD_CACHE
73 #define CONFIG_CMD_DATE
74 #define CONFIG_CMD_PING
77 * Miscellaneous configurable options
79 #define CONFIG_SYS_LONGHELP /* undef to save memory */
80 #define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
81 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
83 /* Print Buffer Size */
84 #define CONFIG_SYS_PBSIZE \
85 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
87 /* max number of command args */
88 #define CONFIG_SYS_MAXARGS 16
90 /* Boot Argument Buffer Size */
91 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
94 * Size of malloc() pool
96 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
99 * SDRAM controller configuration
101 #define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
102 FTSDMC020_TP0_TRP(1) | \
103 FTSDMC020_TP0_TRCD(1) | \
104 FTSDMC020_TP0_TRF(3) | \
105 FTSDMC020_TP0_TWR(1) | \
106 FTSDMC020_TP0_TCL(2))
108 #define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
109 FTSDMC020_TP1_INI_REFT(8) | \
110 FTSDMC020_TP1_REF_INTV(0x180))
112 #define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
113 FTSDMC020_BANK_DDW_X16 | \
114 FTSDMC020_BANK_DSZ_256M | \
115 FTSDMC020_BANK_MBW_32 | \
116 FTSDMC020_BANK_SIZE_64M)
119 * Physical Memory Map
121 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
122 #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
123 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
125 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
126 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
127 GENERATED_GBL_DATA_SIZE)
130 * Load address and memory test area should agree with
131 * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
133 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
135 /* memtest works on 63 MB in DRAM */
136 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
137 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
139 #define CONFIG_SYS_TEXT_BASE 0
142 * Static memory controller configuration
145 #define CONFIG_FTSMC020
146 #include <faraday/ftsmc020.h>
148 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
149 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
150 FTSMC020_BANK_SIZE_1M | \
153 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
154 FTSMC020_TPR_AST(3) | \
155 FTSMC020_TPR_CTW(3) | \
156 FTSMC020_TPR_ATI(0xf) | \
157 FTSMC020_TPR_AT2(3) | \
158 FTSMC020_TPR_WTC(3) | \
159 FTSMC020_TPR_AHT(3) | \
160 FTSMC020_TPR_TRNA(0xf))
162 #define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
163 FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
164 FTSMC020_BANK_SIZE_32M | \
165 FTSMC020_BANK_MBW_32)
167 #define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
168 FTSMC020_TPR_CTW(3) | \
169 FTSMC020_TPR_ATI(0xf) | \
170 FTSMC020_TPR_AT2(3) | \
171 FTSMC020_TPR_WTC(3) | \
172 FTSMC020_TPR_AHT(3) | \
173 FTSMC020_TPR_TRNA(0xf))
175 #define CONFIG_SYS_FTSMC020_CONFIGS { \
176 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
177 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
181 * FLASH and environment organization
184 /* use CFI framework */
185 #define CONFIG_SYS_FLASH_CFI
186 #define CONFIG_FLASH_CFI_DRIVER
189 #define CONFIG_FLASH_CFI_LEGACY
190 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
192 #define PHYS_FLASH_1 0x00000000
193 #define PHYS_FLASH_2 0x00400000
194 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
195 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
197 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
199 /* max number of memory banks */
200 #define CONFIG_SYS_MAX_FLASH_BANKS 2
202 /* max number of sectors on one chip */
203 #define CONFIG_SYS_MAX_FLASH_SECT 512
205 #undef CONFIG_SYS_FLASH_EMPTY_INFO
208 #define CONFIG_ENV_IS_IN_FLASH
209 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
210 #define CONFIG_ENV_SIZE 0x20000
212 #endif /* __CONFIG_H */