include/configs/a320evb.h

   1 /*
   2  * (C) Copyright 2009 Faraday Technology
   3  * Po-Yu Chuang <ratbert@faraday-tech.com>
   4  *
   5  * Configuation settings for the Faraday A320 board.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <asm/arch/a320.h>
  14
  15 /*
  16  * mach-type definition
  17  */
  18 #define MACH_TYPE_FARADAY       758
  19 #define CONFIG_MACH_TYPE        MACH_TYPE_FARADAY
  20
  21 /*
  22  * Linux kernel tagged list
  23  */
  24 #define CONFIG_CMDLINE_TAG
  25 #define CONFIG_SETUP_MEMORY_TAGS
  26
  27 /*
  28  * CPU and Board Configuration Options
  29  */
  30 #undef CONFIG_SKIP_LOWLEVEL_INIT
  31
  32 /*
  33  * Power Management Unit
  34  */
  35 #define CONFIG_FTPMU010_POWER
  36
  37 /*
  38  * Timer
  39  */
  40
  41 /*
  42  * Real Time Clock
  43  */
  44 #define CONFIG_RTC_FTRTC010
  45
  46 /*
  47  * Serial console configuration
  48  */
  49
  50 /* FTUART is a high speed NS 16C550A compatible UART */
  51 #define CONFIG_BAUDRATE                 38400
  52 #define CONFIG_CONS_INDEX               1
  53 #define CONFIG_SYS_NS16550
  54 #define CONFIG_SYS_NS16550_SERIAL
  55 #define CONFIG_SYS_NS16550_COM1         0x98200000
  56 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  57 #define CONFIG_SYS_NS16550_CLK          18432000
  58
  59 /*
  60  * Ethernet
  61  */
  62 #define CONFIG_FTMAC100
  63
  64 #define CONFIG_BOOTDELAY        3
  65
  66 /*
  67  * Command line configuration.
  68  */
  69 #include <config_cmd_default.h>
  70
  71 #define CONFIG_CMD_CACHE
  72 #define CONFIG_CMD_DATE
  73 #define CONFIG_CMD_PING
  74
  75 /*
  76  * Miscellaneous configurable options
  77  */
  78 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
  79 #define CONFIG_SYS_PROMPT       "A320 # "       /* Monitor Command Prompt */
  80 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
  81
  82 /* Print Buffer Size */
  83 #define CONFIG_SYS_PBSIZE       \
  84         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  85
  86 /* max number of command args */
  87 #define CONFIG_SYS_MAXARGS      16
  88
  89 /* Boot Argument Buffer Size */
  90 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  91
  92 /*
  93  * Size of malloc() pool
  94  */
  95 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
  96
  97 /*
  98  * SDRAM controller configuration
  99  */
 100 #define CONFIG_SYS_FTSDMC020_TP0        (FTSDMC020_TP0_TRAS(2) |        \
 101                                          FTSDMC020_TP0_TRP(1)  |        \
 102                                          FTSDMC020_TP0_TRCD(1) |        \
 103                                          FTSDMC020_TP0_TRF(3)  |        \
 104                                          FTSDMC020_TP0_TWR(1)  |        \
 105                                          FTSDMC020_TP0_TCL(2))
 106
 107 #define CONFIG_SYS_FTSDMC020_TP1        (FTSDMC020_TP1_INI_PREC(4) |    \
 108                                          FTSDMC020_TP1_INI_REFT(8) |    \
 109                                          FTSDMC020_TP1_REF_INTV(0x180))
 110
 111 #define CONFIG_SYS_FTSDMC020_BANK0_BSR  (FTSDMC020_BANK_ENABLE   |      \
 112                                          FTSDMC020_BANK_DDW_X16  |      \
 113                                          FTSDMC020_BANK_DSZ_256M |      \
 114                                          FTSDMC020_BANK_MBW_32   |      \
 115                                          FTSDMC020_BANK_SIZE_64M)
 116
 117 /*
 118  * Physical Memory Map
 119  */
 120 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
 121 #define PHYS_SDRAM_1            0x10000000      /* SDRAM Bank #1 */
 122 #define PHYS_SDRAM_1_SIZE       0x04000000      /* 64 MB */
 123
 124 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 125 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 126                                         GENERATED_GBL_DATA_SIZE)
 127
 128 /*
 129  * Load address and memory test area should agree with
 130  * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
 131  */
 132 #define CONFIG_SYS_LOAD_ADDR            (PHYS_SDRAM_1 + 0x2000000)
 133
 134 /* memtest works on 63 MB in DRAM */
 135 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
 136 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_1 + 0x3F00000)
 137
 138 #define CONFIG_SYS_TEXT_BASE            0
 139
 140 /*
 141  * Static memory controller configuration
 142  */
 143
 144 #define CONFIG_FTSMC020
 145 #include <faraday/ftsmc020.h>
 146
 147 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 148                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 149                                  FTSMC020_BANK_SIZE_1M            |     \
 150                                  FTSMC020_BANK_MBW_8)
 151
 152 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_RBE      |        \
 153                                  FTSMC020_TPR_AST(3)   |        \
 154                                  FTSMC020_TPR_CTW(3)   |        \
 155                                  FTSMC020_TPR_ATI(0xf) |        \
 156                                  FTSMC020_TPR_AT2(3)   |        \
 157                                  FTSMC020_TPR_WTC(3)   |        \
 158                                  FTSMC020_TPR_AHT(3)   |        \
 159                                  FTSMC020_TPR_TRNA(0xf))
 160
 161 #define FTSMC020_BANK1_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 162                                  FTSMC020_BANK_BASE(PHYS_FLASH_2) |     \
 163                                  FTSMC020_BANK_SIZE_32M           |     \
 164                                  FTSMC020_BANK_MBW_32)
 165
 166 #define FTSMC020_BANK1_TIMING   (FTSMC020_TPR_AST(3)   |        \
 167                                  FTSMC020_TPR_CTW(3)   |        \
 168                                  FTSMC020_TPR_ATI(0xf) |        \
 169                                  FTSMC020_TPR_AT2(3)   |        \
 170                                  FTSMC020_TPR_WTC(3)   |        \
 171                                  FTSMC020_TPR_AHT(3)   |        \
 172                                  FTSMC020_TPR_TRNA(0xf))
 173
 174 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 175         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 176         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 177 }
 178
 179 /*
 180  * FLASH and environment organization
 181  */
 182
 183 /* use CFI framework */
 184 #define CONFIG_SYS_FLASH_CFI
 185 #define CONFIG_FLASH_CFI_DRIVER
 186
 187 /* support JEDEC */
 188 #define CONFIG_FLASH_CFI_LEGACY
 189 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
 190
 191 #define PHYS_FLASH_1                    0x00000000
 192 #define PHYS_FLASH_2                    0x00400000
 193 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 194 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, PHYS_FLASH_2, }
 195
 196 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 197
 198 /* max number of memory banks */
 199 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 200
 201 /* max number of sectors on one chip */
 202 #define CONFIG_SYS_MAX_FLASH_SECT       512
 203
 204 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 205
 206 /* environments */
 207 #define CONFIG_ENV_IS_IN_FLASH
 208 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x60000)
 209 #define CONFIG_ENV_SIZE                 0x20000
 210
 211 #endif  /* __CONFIG_H */