Merge branch 'master' of git://git.denx.de/u-boot-video
[platform/kernel/u-boot.git] / include / configs / a320evb.h
1 /*
2  * (C) Copyright 2009 Faraday Technology
3  * Po-Yu Chuang <ratbert@faraday-tech.com>
4  *
5  * Configuation settings for the Faraday A320 board.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20  */
21
22 #ifndef __CONFIG_H
23 #define __CONFIG_H
24
25 #include <asm/arch/a320.h>
26
27 /*-----------------------------------------------------------------------
28  * CPU and Board Configuration Options
29  */
30 #undef CONFIG_USE_IRQ           /* we don't need IRQ/FIQ stuff */
31
32 #undef CONFIG_SKIP_LOWLEVEL_INIT
33
34 /*-----------------------------------------------------------------------
35  * Power Management Unit
36  */
37 #define CONFIG_FTPMU010_POWER
38
39 /*-----------------------------------------------------------------------
40  * Timer
41  */
42 #define CONFIG_SYS_HZ           1000    /* timer ticks per second */
43
44 /*-----------------------------------------------------------------------
45  * Real Time Clock
46  */
47 #define CONFIG_RTC_FTRTC010
48
49 /*-----------------------------------------------------------------------
50  * Serial console configuration
51  */
52
53 /* FTUART is a high speed NS 16C550A compatible UART */
54 #define CONFIG_BAUDRATE                 38400
55 #define CONFIG_CONS_INDEX               1
56 #define CONFIG_SYS_NS16550
57 #define CONFIG_SYS_NS16550_SERIAL
58 #define CONFIG_SYS_NS16550_COM1         0x98200000
59 #define CONFIG_SYS_NS16550_REG_SIZE     -4
60 #define CONFIG_SYS_NS16550_CLK          18432000
61
62 /* valid baudrates */
63 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
64
65 /*-----------------------------------------------------------------------
66  * Ethernet
67  */
68 #define CONFIG_NET_MULTI
69 #define CONFIG_FTMAC100
70
71 #define CONFIG_BOOTDELAY        3
72
73 /*-----------------------------------------------------------------------
74  * Command line configuration.
75  */
76 #include <config_cmd_default.h>
77
78 #define CONFIG_CMD_CACHE
79 #define CONFIG_CMD_DATE
80 #define CONFIG_CMD_PING
81
82 /*-----------------------------------------------------------------------
83  * Miscellaneous configurable options
84  */
85 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
86 #define CONFIG_SYS_PROMPT       "A320 # "       /* Monitor Command Prompt */
87 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
88
89 /* Print Buffer Size */
90 #define CONFIG_SYS_PBSIZE       \
91         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
92
93 /* max number of command args */
94 #define CONFIG_SYS_MAXARGS      16
95
96 /* Boot Argument Buffer Size */
97 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
98
99 /*-----------------------------------------------------------------------
100  * Stack sizes
101  *
102  * The stack sizes are set up in start.S using the settings below
103  */
104 #define CONFIG_STACKSIZE        (128 * 1024)    /* regular stack */
105 #ifdef CONFIG_USE_IRQ
106 #define CONFIG_STACKSIZE_IRQ    (4 * 1024)      /* IRQ stack */
107 #define CONFIG_STACKSIZE_FIQ    (4 * 1024)      /* FIQ stack */
108 #endif
109
110 /*-----------------------------------------------------------------------
111  * Size of malloc() pool
112  */
113 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
114
115 /*-----------------------------------------------------------------------
116  * size in bytes reserved for initial data
117 */
118
119 /*-----------------------------------------------------------------------
120  * SDRAM controller configuration
121  */
122 #define CONFIG_SYS_FTSDMC020_TP0        (FTSDMC020_TP0_TRAS(2) |        \
123                                          FTSDMC020_TP0_TRP(1)  |        \
124                                          FTSDMC020_TP0_TRCD(1) |        \
125                                          FTSDMC020_TP0_TRF(3)  |        \
126                                          FTSDMC020_TP0_TWR(1)  |        \
127                                          FTSDMC020_TP0_TCL(2))
128
129 #define CONFIG_SYS_FTSDMC020_TP1        (FTSDMC020_TP1_INI_PREC(4) |    \
130                                          FTSDMC020_TP1_INI_REFT(8) |    \
131                                          FTSDMC020_TP1_REF_INTV(0x180))
132
133 #define CONFIG_SYS_FTSDMC020_BANK0_BSR  (FTSDMC020_BANK_ENABLE   |      \
134                                          FTSDMC020_BANK_DDW_X16  |      \
135                                          FTSDMC020_BANK_DSZ_256M |      \
136                                          FTSDMC020_BANK_MBW_32   |      \
137                                          FTSDMC020_BANK_SIZE_64M)
138
139 /*-----------------------------------------------------------------------
140  * Physical Memory Map
141  */
142 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
143 #define PHYS_SDRAM_1            0x10000000      /* SDRAM Bank #1 */
144 #define PHYS_SDRAM_1_SIZE       0x04000000      /* 64 MB */
145
146 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
147 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
148                                         GENERATED_GBL_DATA_SIZE)
149
150 /*
151  * Load address and memory test area should agree with
152  * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
153  */
154 #define CONFIG_SYS_LOAD_ADDR            (PHYS_SDRAM_1 + 0x2000000)
155
156 /* memtest works on 63 MB in DRAM */
157 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
158 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_1 + 0x3F00000)
159
160 #define CONFIG_SYS_TEXT_BASE            0
161
162 /*-----------------------------------------------------------------------
163  * Static memory controller configuration
164  */
165
166 #define CONFIG_FTSMC020
167 #include <faraday/ftsmc020.h>
168
169 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
170                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
171                                  FTSMC020_BANK_SIZE_1M            |     \
172                                  FTSMC020_BANK_MBW_8)
173
174 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_RBE      |        \
175                                  FTSMC020_TPR_AST(3)   |        \
176                                  FTSMC020_TPR_CTW(3)   |        \
177                                  FTSMC020_TPR_ATI(0xf) |        \
178                                  FTSMC020_TPR_AT2(3)   |        \
179                                  FTSMC020_TPR_WTC(3)   |        \
180                                  FTSMC020_TPR_AHT(3)   |        \
181                                  FTSMC020_TPR_TRNA(0xf))
182
183 #define FTSMC020_BANK1_CONFIG   (FTSMC020_BANK_ENABLE             |     \
184                                  FTSMC020_BANK_BASE(PHYS_FLASH_2) |     \
185                                  FTSMC020_BANK_SIZE_32M           |     \
186                                  FTSMC020_BANK_MBW_32)
187
188 #define FTSMC020_BANK1_TIMING   (FTSMC020_TPR_AST(3)   |        \
189                                  FTSMC020_TPR_CTW(3)   |        \
190                                  FTSMC020_TPR_ATI(0xf) |        \
191                                  FTSMC020_TPR_AT2(3)   |        \
192                                  FTSMC020_TPR_WTC(3)   |        \
193                                  FTSMC020_TPR_AHT(3)   |        \
194                                  FTSMC020_TPR_TRNA(0xf))
195
196 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
197         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
198         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
199 }
200
201 /*-----------------------------------------------------------------------
202  * FLASH and environment organization
203  */
204
205 /* use CFI framework */
206 #define CONFIG_SYS_FLASH_CFI
207 #define CONFIG_FLASH_CFI_DRIVER
208
209 /* support JEDEC */
210 #define CONFIG_FLASH_CFI_LEGACY
211 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
212
213 #define PHYS_FLASH_1                    0x00000000
214 #define PHYS_FLASH_2                    0x00400000
215 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
216 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, PHYS_FLASH_2, }
217
218 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
219
220 /* max number of memory banks */
221 #define CONFIG_SYS_MAX_FLASH_BANKS      2
222
223 /* max number of sectors on one chip */
224 #define CONFIG_SYS_MAX_FLASH_SECT       512
225
226 #undef CONFIG_SYS_FLASH_EMPTY_INFO
227
228 /* environments */
229 #define CONFIG_ENV_IS_IN_FLASH
230 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x60000)
231 #define CONFIG_ENV_SIZE                 0x20000
232
233 #endif  /* __CONFIG_H */