include/configs/a320evb.h

   1 /*
   2  * (C) Copyright 2009 Faraday Technology
   3  * Po-Yu Chuang <ratbert@faraday-tech.com>
   4  *
   5  * Configuation settings for the Faraday A320 board.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 #include <asm/arch/a320.h>
  26
  27 /*
  28  * mach-type definition
  29  */
  30 #define MACH_TYPE_FARADAY       758
  31 #define CONFIG_MACH_TYPE        MACH_TYPE_FARADAY
  32
  33 /*
  34  * Linux kernel tagged list
  35  */
  36 #define CONFIG_CMDLINE_TAG
  37 #define CONFIG_SETUP_MEMORY_TAGS
  38
  39 /*
  40  * CPU and Board Configuration Options
  41  */
  42 #undef CONFIG_USE_IRQ           /* we don't need IRQ/FIQ stuff */
  43
  44 #undef CONFIG_SKIP_LOWLEVEL_INIT
  45
  46 /*
  47  * Power Management Unit
  48  */
  49 #define CONFIG_FTPMU010_POWER
  50
  51 /*
  52  * Timer
  53  */
  54 #define CONFIG_SYS_HZ           1000    /* timer ticks per second */
  55
  56 /*
  57  * Real Time Clock
  58  */
  59 #define CONFIG_RTC_FTRTC010
  60
  61 /*
  62  * Serial console configuration
  63  */
  64
  65 /* FTUART is a high speed NS 16C550A compatible UART */
  66 #define CONFIG_BAUDRATE                 38400
  67 #define CONFIG_CONS_INDEX               1
  68 #define CONFIG_SYS_NS16550
  69 #define CONFIG_SYS_NS16550_SERIAL
  70 #define CONFIG_SYS_NS16550_COM1         0x98200000
  71 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  72 #define CONFIG_SYS_NS16550_CLK          18432000
  73
  74 /* valid baudrates */
  75 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  76
  77 /*
  78  * Ethernet
  79  */
  80 #define CONFIG_FTMAC100
  81
  82 #define CONFIG_BOOTDELAY        3
  83
  84 /*
  85  * Command line configuration.
  86  */
  87 #include <config_cmd_default.h>
  88
  89 #define CONFIG_CMD_CACHE
  90 #define CONFIG_CMD_DATE
  91 #define CONFIG_CMD_PING
  92
  93 /*
  94  * Miscellaneous configurable options
  95  */
  96 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
  97 #define CONFIG_SYS_PROMPT       "A320 # "       /* Monitor Command Prompt */
  98 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
  99
 100 /* Print Buffer Size */
 101 #define CONFIG_SYS_PBSIZE       \
 102         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 103
 104 /* max number of command args */
 105 #define CONFIG_SYS_MAXARGS      16
 106
 107 /* Boot Argument Buffer Size */
 108 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 109
 110 /*
 111  * Stack sizes
 112  *
 113  * The stack sizes are set up in start.S using the settings below
 114  */
 115 #define CONFIG_STACKSIZE        (128 * 1024)    /* regular stack */
 116 #ifdef CONFIG_USE_IRQ
 117 #define CONFIG_STACKSIZE_IRQ    (4 * 1024)      /* IRQ stack */
 118 #define CONFIG_STACKSIZE_FIQ    (4 * 1024)      /* FIQ stack */
 119 #endif
 120
 121 /*
 122  * Size of malloc() pool
 123  */
 124 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
 125
 126 /*
 127  * SDRAM controller configuration
 128  */
 129 #define CONFIG_SYS_FTSDMC020_TP0        (FTSDMC020_TP0_TRAS(2) |        \
 130                                          FTSDMC020_TP0_TRP(1)  |        \
 131                                          FTSDMC020_TP0_TRCD(1) |        \
 132                                          FTSDMC020_TP0_TRF(3)  |        \
 133                                          FTSDMC020_TP0_TWR(1)  |        \
 134                                          FTSDMC020_TP0_TCL(2))
 135
 136 #define CONFIG_SYS_FTSDMC020_TP1        (FTSDMC020_TP1_INI_PREC(4) |    \
 137                                          FTSDMC020_TP1_INI_REFT(8) |    \
 138                                          FTSDMC020_TP1_REF_INTV(0x180))
 139
 140 #define CONFIG_SYS_FTSDMC020_BANK0_BSR  (FTSDMC020_BANK_ENABLE   |      \
 141                                          FTSDMC020_BANK_DDW_X16  |      \
 142                                          FTSDMC020_BANK_DSZ_256M |      \
 143                                          FTSDMC020_BANK_MBW_32   |      \
 144                                          FTSDMC020_BANK_SIZE_64M)
 145
 146 /*
 147  * Physical Memory Map
 148  */
 149 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
 150 #define PHYS_SDRAM_1            0x10000000      /* SDRAM Bank #1 */
 151 #define PHYS_SDRAM_1_SIZE       0x04000000      /* 64 MB */
 152
 153 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 154 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 155                                         GENERATED_GBL_DATA_SIZE)
 156
 157 /*
 158  * Load address and memory test area should agree with
 159  * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
 160  */
 161 #define CONFIG_SYS_LOAD_ADDR            (PHYS_SDRAM_1 + 0x2000000)
 162
 163 /* memtest works on 63 MB in DRAM */
 164 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
 165 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_1 + 0x3F00000)
 166
 167 #define CONFIG_SYS_TEXT_BASE            0
 168
 169 /*
 170  * Static memory controller configuration
 171  */
 172
 173 #define CONFIG_FTSMC020
 174 #include <faraday/ftsmc020.h>
 175
 176 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 177                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 178                                  FTSMC020_BANK_SIZE_1M            |     \
 179                                  FTSMC020_BANK_MBW_8)
 180
 181 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_RBE      |        \
 182                                  FTSMC020_TPR_AST(3)   |        \
 183                                  FTSMC020_TPR_CTW(3)   |        \
 184                                  FTSMC020_TPR_ATI(0xf) |        \
 185                                  FTSMC020_TPR_AT2(3)   |        \
 186                                  FTSMC020_TPR_WTC(3)   |        \
 187                                  FTSMC020_TPR_AHT(3)   |        \
 188                                  FTSMC020_TPR_TRNA(0xf))
 189
 190 #define FTSMC020_BANK1_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 191                                  FTSMC020_BANK_BASE(PHYS_FLASH_2) |     \
 192                                  FTSMC020_BANK_SIZE_32M           |     \
 193                                  FTSMC020_BANK_MBW_32)
 194
 195 #define FTSMC020_BANK1_TIMING   (FTSMC020_TPR_AST(3)   |        \
 196                                  FTSMC020_TPR_CTW(3)   |        \
 197                                  FTSMC020_TPR_ATI(0xf) |        \
 198                                  FTSMC020_TPR_AT2(3)   |        \
 199                                  FTSMC020_TPR_WTC(3)   |        \
 200                                  FTSMC020_TPR_AHT(3)   |        \
 201                                  FTSMC020_TPR_TRNA(0xf))
 202
 203 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 204         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 205         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 206 }
 207
 208 /*
 209  * FLASH and environment organization
 210  */
 211
 212 /* use CFI framework */
 213 #define CONFIG_SYS_FLASH_CFI
 214 #define CONFIG_FLASH_CFI_DRIVER
 215
 216 /* support JEDEC */
 217 #define CONFIG_FLASH_CFI_LEGACY
 218 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
 219
 220 #define PHYS_FLASH_1                    0x00000000
 221 #define PHYS_FLASH_2                    0x00400000
 222 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 223 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, PHYS_FLASH_2, }
 224
 225 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 226
 227 /* max number of memory banks */
 228 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 229
 230 /* max number of sectors on one chip */
 231 #define CONFIG_SYS_MAX_FLASH_SECT       512
 232
 233 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 234
 235 /* environments */
 236 #define CONFIG_ENV_IS_IN_FLASH
 237 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x60000)
 238 #define CONFIG_ENV_SIZE                 0x20000
 239
 240 #endif  /* __CONFIG_H */