2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * xpedite5200 board configuration file
31 * High Level Configuration Options
33 #define CONFIG_BOOKE 1 /* BOOKE */
34 #define CONFIG_E500 1 /* BOOKE e500 family */
35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
36 #define CONFIG_MPC8548 1
37 #define CONFIG_XPEDITE5200 1
38 #define CONFIG_SYS_BOARD_NAME "XPedite5200"
39 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
41 #ifndef CONFIG_SYS_TEXT_BASE
42 #define CONFIG_SYS_TEXT_BASE 0xfff80000
45 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
46 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
47 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
48 #define CONFIG_PCI1 1 /* PCI controller 1 */
49 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
50 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
56 #define CONFIG_FSL_DDR2
57 #undef CONFIG_FSL_DDR_INTERACTIVE
58 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
59 #define CONFIG_DDR_SPD
60 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
61 #define SPD_EEPROM_ADDRESS 0x54
62 #define CONFIG_NUM_DDR_CONTROLLERS 1
63 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
64 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
65 #define CONFIG_DDR_ECC
66 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
67 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
68 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
69 #define CONFIG_VERY_BIG_RAM
71 #define CONFIG_SYS_CLK_FREQ 66666666
74 * These can be toggled for performance analysis, otherwise use default.
76 #define CONFIG_L2_CACHE /* toggle L2 cache */
77 #define CONFIG_BTB /* toggle branch predition */
78 #define CONFIG_ENABLE_36BIT_PHYS 1
81 * Base addresses -- Note these are effective addresses where the
82 * actual resources get mapped (not physical addresses)
84 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
85 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
86 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
87 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
92 #define CONFIG_SYS_ALT_MEMTEST
93 #define CONFIG_SYS_MEMTEST_START 0x10000000
94 #define CONFIG_SYS_MEMTEST_END 0x20000000
98 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
99 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
100 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
101 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
102 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
103 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
104 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
105 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
108 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
111 * NAND flash configuration
113 #define CONFIG_SYS_NAND_BASE 0xef800000
114 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
115 #define CONFIG_SYS_MAX_NAND_DEVICE 1
116 #define CONFIG_NAND_ACTL
117 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
118 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
119 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
120 #define CONFIG_SYS_NAND_ACTL_DELAY 25
123 * NOR flash configuration
125 #define CONFIG_SYS_FLASH_BASE 0xfc000000
126 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
127 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
128 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
129 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
130 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
131 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
132 #define CONFIG_FLASH_CFI_DRIVER
133 #define CONFIG_SYS_FLASH_CFI
134 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
135 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
136 {0xfbf40000, 0xc0000} }
137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
140 * Chip select configuration
142 /* NOR Flash 0 on CS0 */
143 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
146 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
150 /* NOR Flash 1 on CS1 */
151 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
154 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
156 /* NAND flash on CS2 */
157 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
161 /* NAND flash on CS2 */
162 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
170 /* NAND flash on CS3 */
171 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
174 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
177 * Use L1 as initial stack
179 #define CONFIG_SYS_INIT_RAM_LOCK 1
180 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
181 #define CONFIG_SYS_INIT_RAM_END 0x4000
183 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
184 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
185 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
187 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
188 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
193 #define CONFIG_CONS_INDEX 1
194 #define CONFIG_SYS_NS16550
195 #define CONFIG_SYS_NS16550_SERIAL
196 #define CONFIG_SYS_NS16550_REG_SIZE 1
197 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
198 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
199 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
200 #define CONFIG_SYS_BAUDRATE_TABLE \
201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
202 #define CONFIG_BAUDRATE 115200
203 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
204 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
207 * Use the HUSH parser
209 #define CONFIG_SYS_HUSH_PARSER
210 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
213 * Pass open firmware flat tree
215 #define CONFIG_OF_LIBFDT 1
216 #define CONFIG_OF_BOARD_SETUP 1
217 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
222 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
223 #define CONFIG_HARD_I2C /* I2C with hardware support */
224 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
225 #define CONFIG_SYS_I2C_SLAVE 0x7F
226 #define CONFIG_SYS_I2C_OFFSET 0x3000
227 #define CONFIG_SYS_I2C2_OFFSET 0x3100
228 #define CONFIG_I2C_MULTI_BUS
231 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
232 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
234 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
237 #define CONFIG_RTC_M41T11 1
238 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
239 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
242 #define CONFIG_PCA953X
243 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
244 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
245 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
248 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
249 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
250 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
251 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
252 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
253 #define CONFIG_SYS_PCA953X_FLASH_WP 0x20
254 #define CONFIG_SYS_PCA953X_MONARCH 0x40
255 #define CONFIG_SYS_PCA953X_EREADY 0x80
258 #define CONFIG_SYS_PCA953X_P14_IO0 0x01
259 #define CONFIG_SYS_PCA953X_P14_IO1 0x02
260 #define CONFIG_SYS_PCA953X_P14_IO2 0x04
261 #define CONFIG_SYS_PCA953X_P14_IO3 0x08
262 #define CONFIG_SYS_PCA953X_P14_IO4 0x10
263 #define CONFIG_SYS_PCA953X_P14_IO5 0x20
264 #define CONFIG_SYS_PCA953X_P14_IO6 0x40
265 #define CONFIG_SYS_PCA953X_P14_IO7 0x80
269 * Memory space is mapped 1-1, but I/O space must start from 0.
271 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
272 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
273 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
274 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
275 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
276 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
281 #define CONFIG_TSEC_ENET /* tsec ethernet support */
282 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
283 #define CONFIG_NET_MULTI 1
284 #define CONFIG_MII 1 /* MII PHY management */
285 #define CONFIG_ETHPRIME "eTSEC1"
287 #define CONFIG_TSEC1 1
288 #define CONFIG_TSEC1_NAME "eTSEC1"
289 #define TSEC1_FLAGS TSEC_GIGABIT
290 #define TSEC1_PHY_ADDR 1
291 #define TSEC1_PHYIDX 0
292 #define CONFIG_HAS_ETH0
294 #define CONFIG_TSEC2 1
295 #define CONFIG_TSEC2_NAME "eTSEC2"
296 #define TSEC2_FLAGS TSEC_GIGABIT
297 #define TSEC2_PHY_ADDR 2
298 #define TSEC2_PHYIDX 0
299 #define CONFIG_HAS_ETH1
301 #define CONFIG_TSEC3 1
302 #define CONFIG_TSEC3_NAME "eTSEC3"
303 #define TSEC3_FLAGS TSEC_GIGABIT
304 #define TSEC3_PHY_ADDR 3
305 #define TSEC3_PHYIDX 0
306 #define CONFIG_HAS_ETH2
308 #define CONFIG_TSEC4 1
309 #define CONFIG_TSEC4_NAME "eTSEC4"
310 #define TSEC4_FLAGS TSEC_GIGABIT
311 #define TSEC4_PHY_ADDR 4
312 #define TSEC4_PHYIDX 0
313 #define CONFIG_HAS_ETH3
318 #define CONFIG_BOOTP_BOOTFILESIZE
319 #define CONFIG_BOOTP_BOOTPATH
320 #define CONFIG_BOOTP_GATEWAY
323 * Command configuration.
325 #include <config_cmd_default.h>
327 #define CONFIG_CMD_ASKENV
328 #define CONFIG_CMD_DATE
329 #define CONFIG_CMD_DHCP
330 #define CONFIG_CMD_EEPROM
331 #define CONFIG_CMD_ELF
332 #define CONFIG_CMD_SAVEENV
333 #define CONFIG_CMD_FLASH
334 #define CONFIG_CMD_I2C
335 #define CONFIG_CMD_JFFS2
336 #define CONFIG_CMD_MII
337 #define CONFIG_CMD_NAND
338 #define CONFIG_CMD_NET
339 #define CONFIG_CMD_PCA953X
340 #define CONFIG_CMD_PCA953X_INFO
341 #define CONFIG_CMD_PCI
342 #define CONFIG_CMD_PING
343 #define CONFIG_CMD_SNTP
344 #define CONFIG_CMD_REGINFO
347 * Miscellaneous configurable options
349 #define CONFIG_SYS_LONGHELP /* undef to save memory */
350 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
351 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
352 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
353 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
354 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
355 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
356 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
357 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
358 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
359 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
360 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
361 #define CONFIG_PANIC_HANG /* do not reset board on panic */
362 #define CONFIG_PREBOOT /* enable preboot variable */
364 #define CONFIG_FIT_VERBOSE 1
365 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
366 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
369 * For booting Linux, the board info and command line data
370 * have to be in the first 16 MB of memory, since this is
371 * the maximum mapped by the Linux kernel during initialization.
373 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
374 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
379 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
380 #define BOOTFLAG_WARM 0x02 /* Software reboot */
383 * Environment Configuration
385 #define CONFIG_ENV_IS_IN_FLASH 1
386 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
387 #define CONFIG_ENV_SIZE 0x8000
388 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
392 * fff80000 - ffffffff Pri U-Boot (512 KB)
393 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
394 * fff00000 - fff3ffff Pri FDT (256KB)
395 * fef00000 - ffefffff Pri OS image (16MB)
396 * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
398 * fbf80000 - fbffffff Sec U-Boot (512 KB)
399 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
400 * fbf00000 - fbf3ffff Sec FDT (256KB)
401 * faf00000 - fbefffff Sec OS image (16MB)
402 * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
404 #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
405 #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000)
406 #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
407 #define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000)
408 #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
409 #define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000)
411 #define CONFIG_PROG_UBOOT1 \
412 "$download_cmd $loadaddr $ubootfile; " \
413 "if test $? -eq 0; then " \
414 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
415 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
416 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
417 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
418 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
419 "if test $? -ne 0; then " \
420 "echo PROGRAM FAILED; " \
422 "echo PROGRAM SUCCEEDED; " \
425 "echo DOWNLOAD FAILED; " \
428 #define CONFIG_PROG_UBOOT2 \
429 "$download_cmd $loadaddr $ubootfile; " \
430 "if test $? -eq 0; then " \
431 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
432 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
433 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
434 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
435 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
436 "if test $? -ne 0; then " \
437 "echo PROGRAM FAILED; " \
439 "echo PROGRAM SUCCEEDED; " \
442 "echo DOWNLOAD FAILED; " \
445 #define CONFIG_BOOT_OS_NET \
446 "$download_cmd $osaddr $osfile; " \
447 "if test $? -eq 0; then " \
448 "if test -n $fdtaddr; then " \
449 "$download_cmd $fdtaddr $fdtfile; " \
450 "if test $? -eq 0; then " \
451 "bootm $osaddr - $fdtaddr; " \
453 "echo FDT DOWNLOAD FAILED; " \
459 "echo OS DOWNLOAD FAILED; " \
462 #define CONFIG_PROG_OS1 \
463 "$download_cmd $osaddr $osfile; " \
464 "if test $? -eq 0; then " \
465 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
466 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
467 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
468 "if test $? -ne 0; then " \
469 "echo OS PROGRAM FAILED; " \
471 "echo OS PROGRAM SUCCEEDED; " \
474 "echo OS DOWNLOAD FAILED; " \
477 #define CONFIG_PROG_OS2 \
478 "$download_cmd $osaddr $osfile; " \
479 "if test $? -eq 0; then " \
480 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
481 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
482 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
483 "if test $? -ne 0; then " \
484 "echo OS PROGRAM FAILED; " \
486 "echo OS PROGRAM SUCCEEDED; " \
489 "echo OS DOWNLOAD FAILED; " \
492 #define CONFIG_PROG_FDT1 \
493 "$download_cmd $fdtaddr $fdtfile; " \
494 "if test $? -eq 0; then " \
495 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
496 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
497 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
498 "if test $? -ne 0; then " \
499 "echo FDT PROGRAM FAILED; " \
501 "echo FDT PROGRAM SUCCEEDED; " \
504 "echo FDT DOWNLOAD FAILED; " \
507 #define CONFIG_PROG_FDT2 \
508 "$download_cmd $fdtaddr $fdtfile; " \
509 "if test $? -eq 0; then " \
510 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
511 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
512 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
513 "if test $? -ne 0; then " \
514 "echo FDT PROGRAM FAILED; " \
516 "echo FDT PROGRAM SUCCEEDED; " \
519 "echo FDT DOWNLOAD FAILED; " \
522 #define CONFIG_EXTRA_ENV_SETTINGS \
524 "download_cmd=tftp\0" \
525 "console_args=console=ttyS0,115200\0" \
526 "root_args=root=/dev/nfs rw\0" \
527 "misc_args=ip=on\0" \
528 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
529 "bootfile=/home/user/file\0" \
530 "osfile=/home/user/uImage-XPedite5200\0" \
531 "fdtfile=/home/user/xpedite5200.dtb\0" \
532 "ubootfile=/home/user/u-boot.bin\0" \
534 "osaddr=0x1000000\0" \
535 "loadaddr=0x1000000\0" \
536 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
537 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
538 "prog_os1="CONFIG_PROG_OS1"\0" \
539 "prog_os2="CONFIG_PROG_OS2"\0" \
540 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
541 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
542 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
543 "bootcmd_flash1=run set_bootargs; " \
544 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
545 "bootcmd_flash2=run set_bootargs; " \
546 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
547 "bootcmd=run bootcmd_flash1\0"
548 #endif /* __CONFIG_H */