2 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * config for XPedite1000 from XES Inc.
25 * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
26 * (C) Copyright 2003 Sandburst Corporation
27 * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
33 /* High Level Configuration Options */
34 #define CONFIG_XPEDITE1000 1
35 #define CONFIG_SYS_BOARD_NAME "XPedite1000"
36 #define CONFIG_4xx 1 /* ... PPC4xx family */
38 #define CONFIG_440GX 1 /* 440 GX */
39 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
40 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
45 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
46 #define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
47 #define CONFIG_VERY_BIG_RAM 1
50 * Base addresses -- Note these are effective addresses where the
51 * actual resources get mapped (not physical addresses)
53 #define CONFIG_SYS_SDRAM_BASE 0x00000000
54 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
55 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
56 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
57 #define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
58 #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
59 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
60 #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
61 #define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
66 #define CONFIG_SYS_ALT_MEMTEST
67 #define CONFIG_SYS_MEMTEST_START 0x0400000
68 #define CONFIG_SYS_MEMTEST_END 0x0C00000
71 #define CONFIG_POST (CONFIG_SYS_POST_RTC | \
77 #define USR_LED0 0x00000080
78 #define USR_LED1 0x00000100
79 #define USR_LED2 0x00000200
80 #define USR_LED3 0x00000400
83 extern unsigned long in32(unsigned int);
84 extern void out32(unsigned int, unsigned long);
86 #define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
87 #define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
88 #define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
89 #define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
91 #define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
92 #define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
93 #define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
94 #define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
98 * Use internal SRAM for initial stack
100 #define CONFIG_SYS_TEMP_STACK_OCM 1
101 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
102 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
103 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
104 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
105 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
106 #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
107 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
109 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
110 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
115 #define CONFIG_SYS_BAUDRATE_TABLE \
116 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
117 #define CONFIG_BAUDRATE 115200
118 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
119 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
122 * Use the HUSH parser
124 #define CONFIG_SYS_HUSH_PARSER
125 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
128 * NOR flash configuration
130 #define CONFIG_SYS_MAX_FLASH_BANKS 3
131 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 }
132 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
133 #define CONFIG_FLASH_CFI_DRIVER
134 #define CONFIG_SYS_FLASH_CFI
135 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
136 #define CONFIG_SYS_FLASH_QUIET_TEST /* MirrorBit flashes are optional */
137 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
138 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
143 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
144 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
145 #define CONFIG_SYS_I2C_SLAVE 0x7f
146 #define CONFIG_I2C_MULTI_BUS
149 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
150 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
151 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
152 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
154 /* I2C RTC: STMicro M41T00 */
155 #define CONFIG_RTC_M41T11 1
156 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
157 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
163 #define CONFIG_PCI /* include pci support */
164 #define CONFIG_PCI_PNP /* do pci plug-and-play */
165 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
166 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
168 /* Board-specific PCI */
169 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
170 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
171 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
172 #define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
177 #define CONFIG_PPC4xx_EMAC
178 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
179 #define CONFIG_NET_MULTI 1
180 #define CONFIG_MII 1 /* MII PHY management */
181 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
182 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
183 #define CONFIG_ETHPRIME "ppc_4xx_eth2"
184 #define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */
185 #define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
186 #define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
187 #define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
188 #define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
191 #define CONFIG_BOOTP_BOOTFILESIZE
192 #define CONFIG_BOOTP_BOOTPATH
193 #define CONFIG_BOOTP_GATEWAY
194 #define CONFIG_BOOTP_HOSTNAME
197 * Command configuration
199 #include <config_cmd_default.h>
201 #define CONFIG_CMD_ASKENV
202 #define CONFIG_CMD_DATE
203 #define CONFIG_CMD_DHCP
204 #define CONFIG_CMD_EEPROM
205 #define CONFIG_CMD_ELF
206 #define CONFIG_CMD_FLASH
207 #define CONFIG_CMD_I2C
208 #define CONFIG_CMD_IRQ
209 #define CONFIG_CMD_JFFS2
210 #define CONFIG_CMD_MII
211 #define CONFIG_CMD_NET
212 #define CONFIG_CMD_PCI
213 #define CONFIG_CMD_PING
214 #define CONFIG_CMD_SAVEENV
215 #define CONFIG_CMD_SNTP
218 * Miscellaneous configurable options
220 #define CONFIG_SYS_LONGHELP /* undef to save memory */
221 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
222 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
223 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
224 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
225 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
226 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
227 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
228 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
229 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
230 #define CONFIG_PANIC_HANG /* do not reset board on panic */
231 #define CONFIG_PREBOOT /* enable preboot variable */
233 #define CONFIG_FIT_VERBOSE 1
234 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
235 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
238 * For booting Linux, the board info and command line data
239 * have to be in the first 8 MB of memory, since this is
240 * the maximum mapped by the Linux kernel during initialization.
242 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
247 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
248 #define BOOTFLAG_WARM 0x02 /* Software reboot */
251 * Environment Configuration
253 #define CONFIG_ENV_IS_IN_FLASH 1
254 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
255 #define CONFIG_ENV_SIZE 0x8000
256 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
260 * fff80000 - ffffffff U-Boot (512 KB)
261 * fff40000 - fff7ffff U-Boot Environment (256 KB)
262 * fff00000 - fff3ffff FDT (256KB)
263 * ffc00000 - ffefffff OS image (3MB)
264 * ff000000 - ffbfffff OS Use/Filesystem (12MB)
267 #define CONFIG_UBOOT_ENV_ADDR MK_STR(TEXT_BASE)
268 #define CONFIG_FDT_ENV_ADDR MK_STR(0xfff00000)
269 #define CONFIG_OS_ENV_ADDR MK_STR(0xffc00000)
271 #define CONFIG_PROG_UBOOT \
272 "$download_cmd $loadaddr $ubootfile; " \
273 "if test $? -eq 0; then " \
274 "protect off "CONFIG_UBOOT_ENV_ADDR" +80000; " \
275 "erase "CONFIG_UBOOT_ENV_ADDR" +80000; " \
276 "cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; " \
277 "protect on "CONFIG_UBOOT_ENV_ADDR" +80000; " \
278 "cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; " \
279 "if test $? -ne 0; then " \
280 "echo PROGRAM FAILED; " \
282 "echo PROGRAM SUCCEEDED; " \
285 "echo DOWNLOAD FAILED; " \
288 #define CONFIG_BOOT_OS_NET \
289 "$download_cmd $osaddr $osfile; " \
290 "if test $? -eq 0; then " \
291 "if test -n $fdtaddr; then " \
292 "$download_cmd $fdtaddr $fdtfile; " \
293 "if test $? -eq 0; then " \
294 "bootm $osaddr - $fdtaddr; " \
296 "echo FDT DOWNLOAD FAILED; " \
302 "echo OS DOWNLOAD FAILED; " \
305 #define CONFIG_PROG_OS \
306 "$download_cmd $osaddr $osfile; " \
307 "if test $? -eq 0; then " \
308 "erase "CONFIG_OS_ENV_ADDR" +$filesize; " \
309 "cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
310 "cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
311 "if test $? -ne 0; then " \
312 "echo OS PROGRAM FAILED; " \
314 "echo OS PROGRAM SUCCEEDED; " \
317 "echo OS DOWNLOAD FAILED; " \
320 #define CONFIG_PROG_FDT \
321 "$download_cmd $fdtaddr $fdtfile; " \
322 "if test $? -eq 0; then " \
323 "erase "CONFIG_FDT_ENV_ADDR" +$filesize;" \
324 "cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
325 "cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
326 "if test $? -ne 0; then " \
327 "echo FDT PROGRAM FAILED; " \
329 "echo FDT PROGRAM SUCCEEDED; " \
332 "echo FDT DOWNLOAD FAILED; " \
335 #define CONFIG_EXTRA_ENV_SETTINGS \
337 "download_cmd=tftp\0" \
338 "console_args=console=ttyS0,115200\0" \
339 "root_args=root=/dev/nfs rw\0" \
340 "misc_args=ip=on\0" \
341 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
342 "bootfile=/home/user/file\0" \
343 "osfile=/home/user/uImage-XPedite1000\0" \
344 "fdtfile=/home/user/xpedite1000.dtb\0" \
345 "ubootfile=/home/user/u-boot.bin\0" \
347 "osaddr=0x1000000\0" \
348 "loadaddr=0x1000000\0" \
349 "prog_uboot="CONFIG_PROG_UBOOT"\0" \
350 "prog_os="CONFIG_PROG_OS"\0" \
351 "prog_fdt="CONFIG_PROG_FDT"\0" \
352 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
353 "bootcmd_flash=run set_bootargs; " \
354 "bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0" \
355 "bootcmd=run bootcmd_flash\0"
356 #endif /* __CONFIG_H */