3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
19 #define CONFIG_IDENT_STRING " $Name: $"
21 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
22 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
23 #define CONFIG_WUH405 1 /* ...on a WUH405 board */
25 #define CONFIG_SYS_TEXT_BASE 0xFFFC0000
27 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
28 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
30 #define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
32 #define CONFIG_BAUDRATE 9600
33 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
35 #undef CONFIG_BOOTARGS
36 #undef CONFIG_BOOTCOMMAND
38 #define CONFIG_PREBOOT /* enable preboot variable */
40 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
41 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
43 #define CONFIG_PPC4xx_EMAC
44 #define CONFIG_MII 1 /* MII PHY management */
45 #define CONFIG_PHY_ADDR 0 /* PHY address */
46 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
48 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
54 #define CONFIG_BOOTP_BOOTFILESIZE
55 #define CONFIG_BOOTP_BOOTPATH
56 #define CONFIG_BOOTP_GATEWAY
57 #define CONFIG_BOOTP_HOSTNAME
61 * Command line configuration.
63 #include <config_cmd_default.h>
65 #define CONFIG_CMD_DHCP
66 #define CONFIG_CMD_IRQ
67 #define CONFIG_CMD_ELF
68 #define CONFIG_CMD_NAND
69 #define CONFIG_CMD_DATE
70 #define CONFIG_CMD_I2C
71 #define CONFIG_CMD_MII
72 #define CONFIG_CMD_PING
73 #define CONFIG_CMD_EEPROM
76 #undef CONFIG_WATCHDOG /* watchdog disabled */
78 #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
79 #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
81 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
84 * Miscellaneous configurable options
86 #define CONFIG_SYS_LONGHELP /* undef to save memory */
88 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
90 #if defined(CONFIG_CMD_KGDB)
91 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
93 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
95 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
96 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
97 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
99 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
101 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
103 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
104 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
106 #define CONFIG_CONS_INDEX 2 /* Use UART1 */
107 #define CONFIG_SYS_NS16550
108 #define CONFIG_SYS_NS16550_SERIAL
109 #define CONFIG_SYS_NS16550_REG_SIZE 1
110 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
112 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
113 #define CONFIG_SYS_BASE_BAUD 691200
115 /* The following table includes the supported baudrates */
116 #define CONFIG_SYS_BAUDRATE_TABLE \
117 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
118 57600, 115200, 230400, 460800, 921600 }
120 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
121 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
123 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
125 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
127 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
129 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
131 /*-----------------------------------------------------------------------
133 *-----------------------------------------------------------------------
135 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
136 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
137 #define NAND_BIG_DELAY_US 25
139 #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
140 #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
141 #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
142 #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
144 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
146 /*-----------------------------------------------------------------------
148 *-----------------------------------------------------------------------
150 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
151 #define PCI_HOST_FORCE 1 /* configure as pci host */
152 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
154 #define CONFIG_PCI /* include pci support */
155 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
156 #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
157 #undef CONFIG_PCI_PNP /* do pci plug-and-play */
158 /* resource configuration */
160 #undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
162 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
163 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
164 #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
165 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
166 #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
167 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
168 #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
169 #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
170 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
172 /*-----------------------------------------------------------------------
173 * Start addresses for the final memory configuration
174 * (Set up by the startup code)
175 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
177 #define CONFIG_SYS_SDRAM_BASE 0x00000000
178 #define CONFIG_SYS_FLASH_BASE 0xFFFC0000
179 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
180 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
181 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
184 * For booting Linux, the board info and command line data
185 * have to be in the first 8 MB of memory, since this is
186 * the maximum mapped by the Linux kernel during initialization.
188 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
189 /*-----------------------------------------------------------------------
192 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
193 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
195 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
196 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
198 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
199 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
200 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
202 * The following defines are added for buggy IOP480 byte interface.
203 * All other boards should use the standard values (CPCI405 etc.)
205 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
206 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
207 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
209 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
211 #if 0 /* test-only */
212 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
213 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
216 /*-----------------------------------------------------------------------
217 * Environment Variable setup
219 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
220 #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
221 #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
222 /* total size of a CAT24WC16 is 2048 bytes */
224 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
225 #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
227 /*-----------------------------------------------------------------------
228 * I2C EEPROM (CAT24WC16) for environment
230 #define CONFIG_SYS_I2C
231 #define CONFIG_SYS_I2C_PPC4XX
232 #define CONFIG_SYS_I2C_PPC4XX_CH0
233 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
234 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
236 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
237 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
238 /* mask of address bits that overflow into the "EEPROM chip address" */
239 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
241 /* 16 byte page write mode using*/
242 /* last 4 bits of the address */
243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
246 * Init Memory Controller:
248 * BR0/1 and OR0/1 (FLASH)
251 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
253 /*-----------------------------------------------------------------------
254 * External Bus Controller (EBC) Setup
257 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
258 #define CONFIG_SYS_EBC_PB0AP 0x92015480
259 /*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
260 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
262 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
263 #define CONFIG_SYS_EBC_PB1AP 0x92015480
264 #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
266 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
267 #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
268 #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
270 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
271 #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
272 #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
274 #define CAN_BA 0xF0000000 /* CAN Base Address */
275 #define DUART0_BA 0xF0000400 /* DUART Base Address */
276 #define DUART1_BA 0xF0000408 /* DUART Base Address */
277 #define DUART2_BA 0xF0000410 /* DUART Base Address */
278 #define DUART3_BA 0xF0000418 /* DUART Base Address */
279 #define RTC_BA 0xF0000500 /* RTC Base Address */
280 #define CONFIG_SYS_NAND_BASE 0xF4000000
282 /*-----------------------------------------------------------------------
285 #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
286 #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
288 /* FPGA program pin configuration */
289 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
290 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
291 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
292 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
293 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
295 /*-----------------------------------------------------------------------
296 * Definitions for initial stack pointer and data area (in data cache)
298 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
299 #define CONFIG_SYS_TEMP_STACK_OCM 1
301 /* On Chip Memory location */
302 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
303 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
304 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
305 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
307 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
308 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
310 /*-----------------------------------------------------------------------
311 * Definitions for GPIO setup (PPC405EP specific)
313 * GPIO0[0] - External Bus Controller BLAST output
314 * GPIO0[1-9] - Instruction trace outputs -> GPIO
315 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
316 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
317 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
318 * GPIO0[24-27] - UART0 control signal inputs/outputs
319 * GPIO0[28-29] - UART1 data signal input/output
320 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
322 #define CONFIG_SYS_GPIO0_OSRL 0x40000550
323 #define CONFIG_SYS_GPIO0_OSRH 0x00000110
324 #define CONFIG_SYS_GPIO0_ISR1L 0x00000000
325 #define CONFIG_SYS_GPIO0_ISR1H 0x15555445
326 #define CONFIG_SYS_GPIO0_TSRL 0x00000000
327 #define CONFIG_SYS_GPIO0_TSRH 0x00000000
328 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
330 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
333 * Default speed selection (cpu_plb_opb_ebc) in mhz.
334 * This value will be set if iic boot eprom is disabled.
337 #define PLLMR0_DEFAULT PLLMR0_266_133_66_33
338 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
341 #define PLLMR0_DEFAULT PLLMR0_200_100_50_33
342 #define PLLMR1_DEFAULT PLLMR1_200_100_50_33
345 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
346 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
349 #endif /* __CONFIG_H */