2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_WALNUT405 1 /* ...on a WALNUT405 board */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
44 /*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */
45 #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
47 #ifdef CFG_ENV_IS_IN_NVRAM
48 #undef CFG_ENV_IS_IN_FLASH
50 #ifdef CFG_ENV_IS_IN_FLASH
51 #undef CFG_ENV_IS_IN_NVRAM
55 #define CONFIG_BAUDRATE 9600
56 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
59 #define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
61 #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
64 /* Size (bytes) of interrupt driven serial port buffer.
65 * Set to 0 to use polling instead of interrupts.
66 * Setting to 0 will also disable RTS/CTS handshaking.
69 #define CONFIG_SERIAL_SOFTWARE_FIFO 4000
71 #undef CONFIG_SERIAL_SOFTWARE_FIFO
75 #define CONFIG_BOOTARGS "root=/dev/nfs " \
76 "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
77 "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
79 #define CONFIG_BOOTARGS "root=/dev/hda1 " \
80 "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
84 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
85 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
87 #define CONFIG_MII 1 /* MII PHY management */
88 #define CONFIG_PHY_ADDR 1 /* PHY address */
90 #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
92 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
101 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
102 #include <cmd_confdefs.h>
104 #undef CONFIG_WATCHDOG /* watchdog disabled */
106 #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
109 * Miscellaneous configurable options
111 #define CFG_LONGHELP /* undef to save memory */
112 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
113 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
114 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
116 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
118 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
119 #define CFG_MAXARGS 16 /* max number of command args */
120 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
122 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
123 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
126 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
127 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
128 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
129 * The Linux BASE_BAUD define should match this configuration.
130 * baseBaud = cpuClock/(uartDivisor*16)
131 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
132 * set Linux BASE_BAUD to 403200.
134 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
135 #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
136 #define CFG_BASE_BAUD 691200
138 /* The following table includes the supported baudrates */
139 #define CFG_BAUDRATE_TABLE \
140 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
142 #define CFG_LOAD_ADDR 0x100000 /* default load address */
143 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
145 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
147 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
148 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
149 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
150 #define CFG_I2C_SLAVE 0x7F
153 /*-----------------------------------------------------------------------
155 *-----------------------------------------------------------------------
157 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
158 #define PCI_HOST_FORCE 1 /* configure as pci host */
159 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
161 #define CONFIG_PCI /* include pci support */
162 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
163 #define CONFIG_PCI_PNP /* do pci plug-and-play */
164 /* resource configuration */
166 #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
167 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
168 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
169 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
170 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
171 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
172 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
173 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
175 /*-----------------------------------------------------------------------
176 * External peripheral base address
177 *-----------------------------------------------------------------------
179 #undef CONFIG_IDE_LED /* no led for ide supported */
180 #undef CONFIG_IDE_RESET /* no reset for ide supported */
182 #define CFG_KEY_REG_BASE_ADDR 0xF0100000
183 #define CFG_IR_REG_BASE_ADDR 0xF0200000
184 #define CFG_FPGA_REG_BASE_ADDR 0xF0300000
186 /*-----------------------------------------------------------------------
187 * Start addresses for the final memory configuration
188 * (Set up by the startup code)
189 * Please note that CFG_SDRAM_BASE _must_ start at 0
191 #define CFG_SDRAM_BASE 0x00000000
192 #define CFG_FLASH_BASE 0xFFF80000
193 #define CFG_MONITOR_BASE CFG_FLASH_BASE
194 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
195 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
198 * For booting Linux, the board info and command line data
199 * have to be in the first 8 MB of memory, since this is
200 * the maximum mapped by the Linux kernel during initialization.
202 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
203 /*-----------------------------------------------------------------------
206 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
207 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
209 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
210 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
212 /* BEG ENVIRONNEMENT FLASH */
213 #ifdef CFG_ENV_IS_IN_FLASH
214 #define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
215 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
216 #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
218 /* END ENVIRONNEMENT FLASH */
219 /*-----------------------------------------------------------------------
222 #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
223 #define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
225 #ifdef CFG_ENV_IS_IN_NVRAM
226 #define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
227 #define CFG_ENV_ADDR \
228 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
230 /*-----------------------------------------------------------------------
231 * Cache Configuration
233 #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
234 #define CFG_CACHELINE_SIZE 32 /* ... */
235 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
236 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
240 * Init Memory Controller:
242 * BR0/1 and OR0/1 (FLASH)
245 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
246 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
249 /* Configuration Port location */
250 #define CONFIG_PORT_ADDR 0xF0000500
252 /*-----------------------------------------------------------------------
253 * Definitions for initial stack pointer and data area (in DPRAM)
255 #define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
257 #define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
258 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
259 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
260 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
261 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
263 /*-----------------------------------------------------------------------
264 * Definitions for Serial Presence Detect EEPROM address
265 * (to get SDRAM settings)
267 #define SPD_EEPROM_ADDRESS 0x50
270 * Internal Definitions
274 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
275 #define BOOTFLAG_WARM 0x02 /* Software reboot */
277 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
278 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
279 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
281 #endif /* __CONFIG_H */