3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405GP 1 /* This is a PPC405GP CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC405 family */
38 #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
39 #define CONFIG_W7OLMG 1 /* ...specifically an LMG */
41 #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
43 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
45 #define CONFIG_BAUDRATE 9600
46 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
49 #define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
51 #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
54 #undef CONFIG_BOOTARGS
56 #define CONFIG_LOADADDR F0080000
58 #define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
59 #define CONFIG_OVERWRITE_ETHADDR_ONCE
60 #define CONFIG_IPADDR 192.168.1.1
61 #define CONFIG_NETMASK 255.255.255.0
62 #define CONFIG_SERVERIP 192.168.1.2
64 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
65 #undef CFG_LOADS_BAUD_CHANGE /* disallow baudrate change */
67 #define CONFIG_MII 1 /* MII PHY management */
68 #define CONFIG_PHY_ADDR 0 /* PHY address */
70 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
71 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
72 #define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */
73 #define CFG_DTT_MAX_TEMP 70
74 #define CFG_DTT_LOW_TEMP -30
75 #define CFG_DTT_HYSTERESIS 3
77 #define CONFIG_COMMANDS \
78 (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
79 CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
80 CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \
83 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
84 #include <cmd_confdefs.h>
86 #undef CONFIG_WATCHDOG /* watchdog disabled */
87 #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
89 #define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
90 #define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
92 * Miscellaneous configurable options
94 #define CFG_LONGHELP /* undef to save memory */
95 #define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
96 #undef CFG_HUSH_PARSER /* No hush parse for U-Boot */
97 #ifdef CFG_HUSH_PARSER
98 #define CFG_PROMPT_HUSH_PS2 "> "
100 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
101 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
103 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
105 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
106 #define CFG_MAXARGS 16 /* max number of command args */
107 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
109 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
110 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
112 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
113 #define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
114 #define CFG_BASE_BAUD 384000
117 /* The following table includes the supported baudrates */
118 #define CFG_BAUDRATE_TABLE {9600}
120 #define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
122 #define CFG_LOAD_ADDR 0x100000 /* default load address */
123 #define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */
125 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
127 /*-----------------------------------------------------------------------
129 *-----------------------------------------------------------------------
131 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
132 #define PCI_HOST_FORCE 1 /* configure as pci host */
133 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
135 #define CONFIG_PCI /* include pci support */
136 #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
137 #define CONFIG_PCI_PNP /* pci plug-and-play */
138 /* resource configuration */
139 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
140 #define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
141 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
142 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
143 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
144 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
145 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
146 #define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
148 /*-----------------------------------------------------------------------
149 * Set up values for external bus controller
151 *-----------------------------------------------------------------------
153 /* use PerWE instead of PCI_INT ( these functions share a pin ) */
154 #define CONFIG_USE_PERWE 1
156 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
157 #define CFG_TEMP_STACK_OCM 1
159 /* bank 0 is boot flash */
160 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
161 #define CFG_W7O_EBC_PB0AP 0x03050440
162 /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
163 #define CFG_W7O_EBC_PB0CR 0xFFE38000
165 /* bank 1 is main flash */
166 /* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
167 #define CFG_EBC_PB1AP 0x04850240
168 /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
169 #define CFG_EBC_PB1CR 0xF00FC000
171 /* bank 2 is RTC/NVRAM */
172 /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
173 #define CFG_EBC_PB2AP 0x03000440
174 /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
175 #define CFG_EBC_PB2CR 0xFC018000
177 /* bank 3 is FPGA 0 */
178 /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
179 #define CFG_EBC_PB3AP 0x02000400
180 /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
181 #define CFG_EBC_PB3CR 0xFD01A000
183 /* bank 4 is SAM 8 bit range */
184 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
185 #define CFG_EBC_PB4AP 0x02840380
186 /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
187 #define CFG_EBC_PB4CR 0xFE878000
189 /* bank 5 is SAM 16 bit range */
190 /* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
191 #define CFG_EBC_PB5AP 0x05040d80
192 /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
193 #define CFG_EBC_PB5CR 0xFD87A000
195 /* bank 6 is unused */
197 #define CFG_EBC_PB6AP 0x00000000
199 #define CFG_EBC_PB6CR 0x00000000
201 /* bank 7 is LED register */
202 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
203 #define CFG_W7O_EBC_PB7AP 0x03050440
204 /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
205 #define CFG_W7O_EBC_PB7CR 0xFE01C000
207 /*-----------------------------------------------------------------------
208 * Start addresses for the final memory configuration
209 * (Set up by the startup code)
210 * Please note that CFG_SDRAM_BASE _must_ start at 0
212 #define CFG_SDRAM_BASE 0x00000000
213 #define CFG_FLASH_BASE 0xFFFC0000
214 #define CFG_MONITOR_BASE CFG_FLASH_BASE
215 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */
216 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
219 * For booting Linux, the board info and command line data
220 * have to be in the first 8 MB of memory, since this is
221 * the maximum mapped by the Linux kernel during initialization.
223 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
224 /*-----------------------------------------------------------------------
227 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
228 #define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
230 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
231 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
232 #define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */
234 #if 1 /* Use NVRAM for environment variables */
235 /*-----------------------------------------------------------------------
238 #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
239 #define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
240 #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
241 #define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
242 /*define CFG_ENV_ADDR \
243 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */
244 #define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR
246 #else /* Use Boot Flash for environment variables */
247 /*-----------------------------------------------------------------------
248 * Flash EEPROM for environment
250 #define CFG_ENV_IS_IN_FLASH 1
251 #define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
252 #define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */
254 #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
257 /*-----------------------------------------------------------------------
258 * I2C EEPROM (ATMEL 24C04N)
260 #define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */
261 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
262 #define CFG_I2C_SLAVE 0x7F
264 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */
265 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
266 #define CFG_EEPROM_PAGE_WRITE_ENABLE
267 #define CFG_EEPROM_PAGE_WRITE_BITS 3
268 #define CFG_I2C_MULTI_EEPROMS
269 /*-----------------------------------------------------------------------
270 * Definitions for Serial Presence Detect EEPROM address
271 * (to get SDRAM settings)
273 #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
275 /*-----------------------------------------------------------------------
276 * Cache Configuration
278 #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
279 #define CFG_CACHELINE_SIZE 32 /* ... */
280 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
281 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
285 * Init Memory Controller:
287 #define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
288 #define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
290 /* On Chip Memory location */
291 #define CFG_OCM_DATA_ADDR 0xF8000000
292 #define CFG_OCM_DATA_SIZE 0x1000
294 /*-----------------------------------------------------------------------
295 * Definitions for initial stack pointer and data area (in RAM)
297 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
298 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
299 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
300 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
301 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
305 * Internal Definitions
309 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
310 #define BOOTFLAG_WARM 0x02 /* Software reboot */
312 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
313 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
314 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
318 * FPGA(s) configuration
320 #define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
321 #define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */
322 #define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
323 #define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
324 #define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
326 #endif /* __CONFIG_H */