include/configs/VoVPN-GW.h

   1 /*
   2  * (C) Copyright 2004
   3  * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
   4  *
   5  * Support for the Elmeg VoVPN Gateway Module
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /* define cpu used */
  14 #define CONFIG_MPC8272                  1
  15
  16 /* define busmode: 8260 */
  17 #undef  CONFIG_BUSMODE_60x
  18
  19 #define CONFIG_SYS_TEXT_BASE            0xfff00000
  20
  21 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  22 #ifdef  CONFIG_CLKIN_66MHz
  23 #define CONFIG_8260_CLKIN               66666666        /* in Hz */
  24 #else
  25 #define CONFIG_8260_CLKIN               100000000       /* in Hz */
  26 #endif
  27
  28 /* call board_early_init_f */
  29 #define CONFIG_BOARD_EARLY_INIT_F       1
  30
  31 /* have misc_init_r() function */
  32 #define CONFIG_MISC_INIT_R              1
  33
  34 /* have reset_phy_r() function */
  35 #define CONFIG_RESET_PHY_R              1
  36
  37 /* have special reset function */
  38 #define CONFIG_HAVE_OWN_RESET           1
  39
  40 /* allow serial and ethaddr to be overwritten */
  41 #define CONFIG_ENV_OVERWRITE
  42
  43 /* watchdog disabled */
  44 #undef  CONFIG_WATCHDOG
  45
  46 /* include support for bzip2 compressed images */
  47 #undef  CONFIG_BZIP2
  48
  49 /* status led */
  50 #undef  CONFIG_STATUS_LED               /* XXX jse */
  51
  52 /* vendor parameter protection */
  53 #define CONFIG_ENV_OVERWRITE
  54
  55 /*
  56  * select serial console configuration
  57  *
  58  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  59  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  60  * for SCC).
  61  */
  62 #define CONFIG_CONS_ON_SMC
  63 #undef  CONFIG_CONS_ON_SCC
  64 #undef  CONFIG_CONS_NONE
  65 #define CONFIG_CONS_INDEX               1
  66
  67 /* serial port default baudrate */
  68 #define CONFIG_BAUDRATE                 115200
  69
  70 /* echo on for serial download  */
  71 #define CONFIG_LOADS_ECHO               1
  72
  73 /* don't allow baudrate change  */
  74 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
  75
  76 /*
  77  * select ethernet configuration
  78  *
  79  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  80  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  81  * for FCC)
  82  *
  83  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  84  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  85  */
  86 #undef  CONFIG_ETHER_ON_SCC
  87 #define CONFIG_ETHER_ON_FCC
  88 #undef  CONFIG_ETHER_NONE
  89
  90 #ifdef  CONFIG_ETHER_ON_FCC
  91
  92 /* which SCC/FCC channel for ethernet */
  93 #define CONFIG_ETHER_INDEX              1
  94
  95 /* Marvell Switch SMI base addr */
  96 #define CONFIG_SYS_PHY_ADDR                     0x10
  97
  98 /* FCC1 RMII REFCLK is CLK10 */
  99 #define CONFIG_SYS_CMXFCR_VALUE         CMXFCR_TF1CS_CLK10
 100 #define CONFIG_SYS_CMXFCR_MASK                  (CMXFCR_FC1|CMXFCR_TF1CS_MSK)
 101
 102 /* BDs and buffers on 60x bus */
 103 #define CONFIG_SYS_CPMFCR_RAMTYPE               0
 104
 105 /* Local Protect, Full duplex, Flowcontrol, RMII */
 106 #define CONFIG_SYS_FCC_PSMR                     (FCC_PSMR_LPB|FCC_PSMR_FDE|\
 107                                          FCC_PSMR_FCE|FCC_PSMR_RMII)
 108
 109 /* bit-bang MII PHY management  */
 110 #define CONFIG_BITBANGMII
 111
 112 #define MDIO_PORT                       1               /* Port B */
 113
 114 #define MDIO_DECLARE            volatile ioport_t *iop = ioport_addr ( \
 115                                         (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 116 #define MDC_DECLARE             MDIO_DECLARE
 117
 118 #define CONFIG_SYS_MDIO_PIN                     0x00002000      /* PB18 */
 119 #define CONFIG_SYS_MDC_PIN                      0x00001000      /* PB19 */
 120 #define MDIO_ACTIVE                     (iop->pdir |=  CONFIG_SYS_MDIO_PIN)
 121 #define MDIO_TRISTATE                   (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
 122 #define MDIO_READ                       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 123 #define MDIO(bit)                       if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
 124                                         else    iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 125 #define MDC(bit)                        if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
 126                                         else    iop->pdat &= ~CONFIG_SYS_MDC_PIN
 127 #define MIIDELAY                        udelay(1)
 128
 129 #endif
 130
 131 /*
 132  * BOOTP options
 133  */
 134 #define CONFIG_BOOTP_BOOTFILESIZE
 135 #define CONFIG_BOOTP_BOOTPATH
 136 #define CONFIG_BOOTP_GATEWAY
 137 #define CONFIG_BOOTP_HOSTNAME
 138
 139
 140 /*
 141  * Command line configuration.
 142  */
 143
 144 #define CONFIG_CMD_BDI
 145 #define CONFIG_CMD_CONSOLE
 146 #define CONFIG_CMD_ECHO
 147 #define CONFIG_CMD_FLASH
 148 #define CONFIG_CMD_IMI
 149 #define CONFIG_CMD_IMLS
 150 #define CONFIG_CMD_LOADB
 151 #define CONFIG_CMD_MEMORY
 152 #define CONFIG_CMD_MISC
 153 #define CONFIG_CMD_NET
 154 #define CONFIG_CMD_PING
 155 #define CONFIG_CMD_RUN
 156 #define CONFIG_CMD_SAVEENV
 157 #define CONFIG_CMD_SOURCE
 158
 159
 160 /*
 161  * boot options & environment
 162  */
 163 #define CONFIG_BOOTDELAY                3
 164 #define CONFIG_BOOTCOMMAND              "run flash_self"
 165 #undef  CONFIG_BOOTARGS
 166 #define CONFIG_EXTRA_ENV_SETTINGS       \
 167 "clean_nv=erase fff20000 ffffffff\0" \
 168 "update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
 169 "update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
 170 "update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
 171 "update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
 172 "flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
 173 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
 174 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
 175 "addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
 176 "net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
 177 "net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
 178 "flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
 179 "flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
 180 "fstype=cramfs\0" \
 181 "rootpath=/root_fs\0" \
 182 "uboot=PPC/u-boot.bin\0" \
 183 "kernel=PPC/uImage\0" \
 184 "kernel_addr=ffe00000\0" \
 185 "fs=PPC/root_fs\0" \
 186 "console=ttyS0\0" \
 187 "netdev=eth0\0" \
 188 "rootdev=31:3\0" \
 189 "ethaddr=00:09:4f:01:02:03\0" \
 190 "ipaddr=10.0.0.201\0" \
 191 "netmask=255.255.255.0\0" \
 192 "serverip=10.0.0.136\0" \
 193 "gatewayip=10.0.0.10\0" \
 194 "hostname=bastard\0" \
 195 ""
 196
 197
 198 /*
 199  * miscellaneous configurable options
 200  */
 201
 202 /* undef to save memory */
 203 #define CONFIG_SYS_LONGHELP
 204
 205 /* monitor command prompt */
 206
 207 /* console i/o buffer size */
 208 #if defined(CONFIG_CMD_KGDB)
 209 #define CONFIG_SYS_CBSIZE                       1024
 210 #else
 211 #define CONFIG_SYS_CBSIZE                       256
 212 #endif
 213
 214 /* print buffer size */
 215 #define CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 216
 217 /* max number of command args */
 218 #define CONFIG_SYS_MAXARGS                      16
 219
 220 /* boot argument buffer size */
 221 #define CONFIG_SYS_BARGSIZE                     CONFIG_SYS_CBSIZE
 222
 223 /* memtest works on */
 224 #define CONFIG_SYS_MEMTEST_START                0x00100000
 225 /* 1 ... 15 MB in DRAM */
 226 #define CONFIG_SYS_MEMTEST_END                  0x00f00000
 227 /* full featured memtest */
 228 #define CONFIG_SYS_ALT_MEMTEST
 229
 230 /* default load address */
 231 #define CONFIG_SYS_LOAD_ADDR                    0x00100000
 232
 233 /* decrementer freq: 1 ms ticks */
 234
 235 /* configure flash */
 236 #define CONFIG_SYS_FLASH_BASE                   0xff800000
 237 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 238 #define CONFIG_SYS_MAX_FLASH_SECT               64
 239 #define CONFIG_SYS_FLASH_SIZE                   8
 240 #undef  CONFIG_SYS_FLASH_16BIT
 241 #define CONFIG_SYS_FLASH_ERASE_TOUT             240000
 242 #define CONFIG_SYS_FLASH_WRITE_TOUT             500
 243 #define CONFIG_SYS_FLASH_LOCK_TOUT              500
 244 #define CONFIG_SYS_FLASH_UNLOCK_TOUT            10000
 245 #define CONFIG_SYS_FLASH_PROTECTION
 246
 247 /* monitor in flash */
 248 #define CONFIG_SYS_MONITOR_OFFSET               0x00700000
 249
 250 /* environment in flash */
 251 #define CONFIG_ENV_IS_IN_FLASH          1
 252 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x00020000)
 253 #define CONFIG_ENV_SIZE                 0x00020000
 254 #define CONFIG_ENV_SECT_SIZE            0x00020000
 255
 256 /*
 257  * Initial memory map for linux
 258  * For booting Linux, the board info and command line data
 259  * have to be in the first 8 MB of memory, since this is
 260  * the maximum mapped by the Linux kernel during initialization.
 261  */
 262 #define CONFIG_SYS_BOOTMAPSZ                    (8 << 20)
 263
 264 /* hard reset configuration words */
 265 #ifdef  CONFIG_CLKIN_66MHz
 266 #define CONFIG_SYS_HRCW_MASTER                  0x04643050
 267 #else
 268 #error NO HRCW FOR 100MHZ SPECIFIED !!!
 269 #endif
 270 #define CONFIG_SYS_HRCW_SLAVE1                  0x00000000
 271 #define CONFIG_SYS_HRCW_SLAVE2                  0x00000000
 272 #define CONFIG_SYS_HRCW_SLAVE3                  0x00000000
 273 #define CONFIG_SYS_HRCW_SLAVE4                  0x00000000
 274 #define CONFIG_SYS_HRCW_SLAVE5                  0x00000000
 275 #define CONFIG_SYS_HRCW_SLAVE6                  0x00000000
 276 #define CONFIG_SYS_HRCW_SLAVE7                  0x00000000
 277
 278 /* internal memory mapped register */
 279 #define CONFIG_SYS_IMMR                 0xF0000000
 280
 281 /* definitions for initial stack pointer and data area (in DPRAM) */
 282 #define CONFIG_SYS_INIT_RAM_ADDR                CONFIG_SYS_IMMR
 283 #define CONFIG_SYS_INIT_RAM_SIZE                0x2000
 284 #define CONFIG_SYS_GBL_DATA_OFFSET              (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 285 #define CONFIG_SYS_INIT_SP_OFFSET               CONFIG_SYS_GBL_DATA_OFFSET
 286
 287 /*
 288  * Start addresses for the final memory configuration
 289  * (Set up by the startup code)
 290  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 291  */
 292 #define CONFIG_SYS_SDRAM_BASE                   0x00000000
 293 #define CONFIG_SYS_SDRAM_SIZE                   (32*1024*1024)
 294 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 295 #define CONFIG_SYS_MONITOR_FLASH                (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
 296 #define CONFIG_SYS_MONITOR_LEN                  0x00020000
 297 #define CONFIG_SYS_MALLOC_LEN                   0x00020000
 298
 299 /* cache configuration */
 300 #define CONFIG_SYS_CACHELINE_SIZE               32      /* for MPC8260 */
 301 #if defined(CONFIG_CMD_KGDB)
 302 #define CONFIG_SYS_CACHELINE_SHIFT              5       /* log base 2 of above */
 303 #endif
 304
 305 /*
 306  * HIDx - Hardware Implementation-dependent Registers
 307  *-----------------------------------------------------------------------
 308  * HID0 also contains cache control - initially enable both caches and
 309  * invalidate contents, then the final state leaves only the instruction
 310  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 311  * but Soft reset does not.
 312  *
 313  * HID1 has only read-only information - nothing to set.
 314  */
 315 #define CONFIG_SYS_HID0_INIT                    (HID0_ICE|HID0_DCE|\
 316                                          HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
 317 #define CONFIG_SYS_HID0_FINAL                   (HID0_IFEM|HID0_ABE)
 318 #define CONFIG_SYS_HID2                 0
 319
 320 /* RMR - reset mode register - turn on checkstop reset enable */
 321 #define CONFIG_SYS_RMR                          RMR_CSRE
 322
 323 /* BCR - bus configuration */
 324 #define CONFIG_SYS_BCR                          0x00000000
 325
 326 /* SIUMCR - siu module configuration */
 327 #define CONFIG_SYS_SIUMCR                       0x4905c000
 328
 329 /* SYPCR - system protection control */
 330 #if defined(CONFIG_WATCHDOG)
 331 #define CONFIG_SYS_SYPCR                        0xffffff87
 332 #else
 333 #define CONFIG_SYS_SYPCR                        0xffffff83
 334 #endif
 335
 336 /* TMCNTSC - time counter status and control */
 337 /* clear interrupts XXX jse */
 338 /*#define CONFIG_SYS_TMCNTSC                    (TMCNTSC_SEC|TMCNTSC_ALR) */
 339 #define CONFIG_SYS_TMCNTSC                      (TMCNTSC_SEC|TMCNTSC_ALR|\
 340                                          TMCNTSC_TCF|TMCNTSC_TCE)
 341
 342 /* PISCR - periodic interrupt status and control */
 343 /* clear interrupts XXX jse */
 344 /*#define CONFIG_SYS_PISCR                      (PISCR_PS) */
 345 #define CONFIG_SYS_PISCR                        (PISCR_PS|PISCR_PTF|PISCR_PTE)
 346
 347 /* SCCR - system clock control */
 348 #define CONFIG_SYS_SCCR                 0x000001a9
 349
 350 /* RCCR - risc controller configuration */
 351 #define CONFIG_SYS_RCCR                 0
 352
 353 /*
 354  * MEMORY MAP
 355  * ----------
 356  * CS0 - FLASH    8MB/8Bit      base=0xff800000 (boot: 0xfe000000, 8x mirrored)
 357  * CS1 - SDRAM   32MB/64Bit     base=0x00000000
 358  * CS2 - DSP/SL1  1MB/16Bit     base=0xf0100000
 359  * CS3 - DSP/SL2  1MB/16Bit     base=0xf0200000
 360  * CS4 - DSP/SL3  1MB/16Bit     base=0xf0300000
 361  * CS5 - DSP/SL4  1MB/16Bit     base=0xf0400000
 362  * CS7 - DPRAM    1KB/8Bit      base=0xf0500000, size=32KB (32x mirrored)
 363  *  x  - IMMR     384KB         base=0xf0000000
 364  */
 365 /* XXX jse 100MHz TODO */
 366 #define CONFIG_SYS_BR0_PRELIM                   0xff800801
 367 #define CONFIG_SYS_OR0_PRELIM                   0xff801e44
 368 #define CONFIG_SYS_BR1_PRELIM                   0x00000041
 369 #define CONFIG_SYS_OR1_PRELIM                   0xfe002ec0
 370 #if 1
 371 #define CONFIG_SYS_BR2_PRELIM                   0xf0101001
 372 #define CONFIG_SYS_OR2_PRELIM                   0xfff00ef4
 373 #define CONFIG_SYS_BR3_PRELIM                   0xf0201001
 374 #define CONFIG_SYS_OR3_PRELIM                   0xfff00ef4
 375 #define CONFIG_SYS_BR4_PRELIM                   0xf0301001
 376 #define CONFIG_SYS_OR4_PRELIM                   0xfff00ef4
 377 #define CONFIG_SYS_BR5_PRELIM                   0xf0401001
 378 #define CONFIG_SYS_OR5_PRELIM                   0xfff00ef4
 379 #else
 380 #define CONFIG_SYS_BR2_PRELIM                   0xf0101081
 381 #define CONFIG_SYS_OR2_PRELIM                   0xfff00104
 382 #define CONFIG_SYS_BR3_PRELIM                   0xf0201081
 383 #define CONFIG_SYS_OR3_PRELIM                   0xfff00104
 384 #define CONFIG_SYS_BR4_PRELIM                   0xf0301081
 385 #define CONFIG_SYS_OR4_PRELIM                   0xfff00104
 386 #define CONFIG_SYS_BR5_PRELIM                   0xf0401081
 387 #define CONFIG_SYS_OR5_PRELIM                   0xfff00104
 388 #endif
 389 #define CONFIG_SYS_BR7_PRELIM                   0xf0500881
 390 #define CONFIG_SYS_OR7_PRELIM                   0xffff8104
 391 #define CONFIG_SYS_MPTPR                        0x2700
 392 #define CONFIG_SYS_PSDMR                        0x822a2452      /* optimal */
 393 /*#define CONFIG_SYS_PSDMR                      0x822a48a3 */   /* relaxed */
 394 #define CONFIG_SYS_PSRT                 0x1a
 395
 396 /* "bad" address */
 397 #define CONFIG_SYS_RESET_ADDRESS                0x40000000
 398
 399 #endif  /* __CONFIG_H */