2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
15 * High Level Configuration Options
18 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
19 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
20 #define CONFIG_VOM405 1 /* ...on a VOM405 board */
22 #define CONFIG_SYS_TEXT_BASE 0xFFFC8000
24 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
25 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
27 #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
29 #define CONFIG_BAUDRATE 9600
30 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
32 #undef CONFIG_BOOTARGS
33 #undef CONFIG_BOOTCOMMAND
35 #define CONFIG_PREBOOT /* enable preboot variable */
37 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
39 #undef CONFIG_HAS_ETH1
41 #define CONFIG_PPC4xx_EMAC
42 #define CONFIG_MII 1 /* MII PHY management */
43 #define CONFIG_PHY_ADDR 0 /* PHY address */
44 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
45 #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
50 #define CONFIG_BOOTP_SUBNETMASK
51 #define CONFIG_BOOTP_GATEWAY
52 #define CONFIG_BOOTP_HOSTNAME
53 #define CONFIG_BOOTP_BOOTPATH
54 #define CONFIG_BOOTP_DNS
55 #define CONFIG_BOOTP_DNS2
56 #define CONFIG_BOOTP_SEND_HOSTNAME
59 * Command line configuration.
61 #include <config_cmd_default.h>
63 #define CONFIG_CMD_DHCP
64 #define CONFIG_CMD_BSP
65 #define CONFIG_CMD_IRQ
66 #define CONFIG_CMD_ELF
67 #define CONFIG_CMD_I2C
68 #define CONFIG_CMD_MII
69 #define CONFIG_CMD_PING
70 #define CONFIG_CMD_EEPROM
72 #define CONFIG_OF_LIBFDT
73 #define CONFIG_OF_BOARD_SETUP
75 #undef CONFIG_WATCHDOG /* watchdog disabled */
77 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
79 #undef CONFIG_PRAM /* no "protected RAM" */
82 * Miscellaneous configurable options
84 #define CONFIG_SYS_LONGHELP /* undef to save memory */
85 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
87 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
89 #if defined(CONFIG_CMD_KGDB)
90 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
92 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
94 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
95 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
96 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
98 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
100 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
102 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
103 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
105 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
106 #define CONFIG_SYS_NS16550
107 #define CONFIG_SYS_NS16550_SERIAL
108 #define CONFIG_SYS_NS16550_REG_SIZE 1
109 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
111 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
112 #define CONFIG_SYS_BASE_BAUD 691200
114 /* The following table includes the supported baudrates */
115 #define CONFIG_SYS_BAUDRATE_TABLE \
116 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
117 57600, 115200, 230400, 460800, 921600 }
119 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
120 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
122 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
124 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
125 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
127 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
129 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
132 * For booting Linux, the board info and command line data
133 * have to be in the first 8 MB of memory, since this is
134 * the maximum mapped by the Linux kernel during initialization.
136 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
140 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
142 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
143 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
145 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
146 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
148 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
149 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
150 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
152 * The following defines are added for buggy IOP480 byte interface.
153 * All other boards should use the standard values (CPCI405 etc.)
155 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
156 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
157 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
159 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
162 * Start addresses for the final memory configuration
163 * (Set up by the startup code)
164 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
166 #define CONFIG_SYS_SDRAM_BASE 0x00000000
167 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
169 #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
170 #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
172 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
173 # define CONFIG_SYS_RAMBOOT 1
175 # undef CONFIG_SYS_RAMBOOT
179 * Environment Variable setup
181 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
182 #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
183 #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
184 /* total size of a CAT24WC16 is 2048 bytes */
186 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
187 #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
190 * I2C EEPROM (CAT24WC16) for environment
192 #define CONFIG_SYS_I2C
193 #define CONFIG_SYS_I2C_PPC4XX
194 #define CONFIG_SYS_I2C_PPC4XX_CH0
195 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
196 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
198 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
199 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
200 /* mask of address bits that overflow into the "EEPROM chip address" */
201 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
202 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
203 /* 16 byte page write mode using*/
204 /* last 4 bits of the address */
205 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
208 * External Bus Controller (EBC) Setup
210 #define CAN_BA 0xF0000000 /* CAN Base Address */
212 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
213 #define CONFIG_SYS_EBC_PB0AP 0x92015480
214 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
216 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
217 #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
218 #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
223 #define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
225 /* FPGA program pin configuration */
226 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
227 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
228 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
229 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
230 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
233 * Definitions for initial stack pointer and data area (in data cache)
235 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
236 #define CONFIG_SYS_TEMP_STACK_OCM 1
238 /* On Chip Memory location */
239 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
240 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
241 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
242 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
244 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
245 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
248 * Definitions for GPIO setup (PPC405EP specific)
250 * GPIO0[0] - External Bus Controller BLAST output
251 * GPIO0[1-9] - Instruction trace outputs -> GPIO
252 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
253 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
254 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
255 * GPIO0[24-27] - UART0 control signal inputs/outputs
256 * GPIO0[28-29] - UART1 data signal input/output
257 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
259 /* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
260 /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
261 /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
262 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
263 #define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
264 #define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
265 #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
266 #define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
267 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
268 #define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
269 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
272 * Default speed selection (cpu_plb_opb_ebc) in mhz.
273 * This value will be set if iic boot eprom is disabled.
275 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
276 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
278 #endif /* __CONFIG_H */