2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_VOH405 1 /* ...on a VOH405 board */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
43 #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
45 #define CONFIG_BAUDRATE 9600
46 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48 #undef CONFIG_BOOTARGS
49 #undef CONFIG_BOOTCOMMAND
51 #define CONFIG_PREBOOT /* enable preboot variable */
53 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
55 #define CONFIG_MII 1 /* MII PHY management */
56 #define CONFIG_PHY_ADDR 0 /* PHY address */
57 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
59 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
61 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
75 #define CONFIG_MAC_PARTITION
76 #define CONFIG_DOS_PARTITION
78 #define CONFIG_SUPPORT_VFAT
80 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
81 #include <cmd_confdefs.h>
83 #undef CONFIG_WATCHDOG /* watchdog disabled */
85 #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
86 #define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
88 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
91 * Miscellaneous configurable options
93 #define CFG_LONGHELP /* undef to save memory */
94 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
96 #undef CFG_HUSH_PARSER /* use "hush" command parser */
97 #ifdef CFG_HUSH_PARSER
98 #define CFG_PROMPT_HUSH_PS2 "> "
101 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
102 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
104 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
106 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
107 #define CFG_MAXARGS 16 /* max number of command args */
108 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
110 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
112 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
114 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
116 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
117 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
119 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
120 #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
121 #define CFG_BASE_BAUD 691200
122 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */
124 /* The following table includes the supported baudrates */
125 #define CFG_BAUDRATE_TABLE \
126 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
127 57600, 115200, 230400, 460800, 921600 }
129 #define CFG_LOAD_ADDR 0x100000 /* default load address */
130 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
132 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
134 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
136 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
138 #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
140 /*-----------------------------------------------------------------------
142 *-----------------------------------------------------------------------
144 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
145 #define SECTORSIZE 512
147 #define ADDR_COLUMN 1
149 #define ADDR_COLUMN_PAGE 3
151 #define NAND_ChipID_UNKNOWN 0x00
152 #define NAND_MAX_FLOORS 1
153 #define NAND_MAX_CHIPS 1
155 #define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
156 #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
157 #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
158 #define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
160 #define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
161 #define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
162 #define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
163 #define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
164 #define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
165 #define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
166 #define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
168 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
169 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
170 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
171 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
173 #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
175 /*-----------------------------------------------------------------------
177 *-----------------------------------------------------------------------
179 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
180 #define PCI_HOST_FORCE 1 /* configure as pci host */
181 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
183 #define CONFIG_PCI /* include pci support */
184 #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
185 #define CONFIG_PCI_PNP /* do pci plug-and-play */
186 /* resource configuration */
188 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
190 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
192 #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
193 #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
194 #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
195 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
196 #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
197 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
198 #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
199 #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
200 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
202 /*-----------------------------------------------------------------------
204 *-----------------------------------------------------------------------
206 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
207 #undef CONFIG_IDE_LED /* no led for ide supported */
208 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
210 #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
211 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
213 #define CONFIG_ATAPI 1 /* ATAPI for Travelstar */
215 #define CFG_ATA_BASE_ADDR 0xF0100000
216 #define CFG_ATA_IDE0_OFFSET 0x0000
217 #define CFG_ATA_IDE1_OFFSET 0x0010
219 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
220 #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
221 #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
224 * For booting Linux, the board info and command line data
225 * have to be in the first 8 MB of memory, since this is
226 * the maximum mapped by the Linux kernel during initialization.
228 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
229 /*-----------------------------------------------------------------------
232 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
234 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
235 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
237 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
238 #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
240 #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
241 #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
242 #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
244 * The following defines are added for buggy IOP480 byte interface.
245 * All other boards should use the standard values (CPCI405 etc.)
247 #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
248 #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
249 #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
251 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
253 #if 0 /* test-only */
254 #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
255 #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
258 /*-----------------------------------------------------------------------
259 * Start addresses for the final memory configuration
260 * (Set up by the startup code)
261 * Please note that CFG_SDRAM_BASE _must_ start at 0
263 #define CFG_SDRAM_BASE 0x00000000
264 #define CFG_FLASH_BASE 0xFFF80000
265 #define CFG_MONITOR_BASE TEXT_BASE
266 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
267 #define CFG_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */
269 #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
270 # define CFG_RAMBOOT 1
275 /*-----------------------------------------------------------------------
276 * Environment Variable setup
278 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
279 #define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
280 #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
281 /* total size of a CAT24WC16 is 2048 bytes */
283 #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
284 #define CFG_NVRAM_SIZE 242 /* NVRAM size */
286 /*-----------------------------------------------------------------------
287 * I2C EEPROM (CAT24WC16) for environment
289 #define CONFIG_HARD_I2C /* I2c with hardware support */
290 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
291 #define CFG_I2C_SLAVE 0x7F
293 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
294 #if 0 /* test-only */
295 /* CAT24WC08/16... */
296 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
297 /* mask of address bits that overflow into the "EEPROM chip address" */
298 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
299 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
300 /* 16 byte page write mode using*/
301 /* last 4 bits of the address */
303 /* CAT24WC32/64... */
304 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
305 /* mask of address bits that overflow into the "EEPROM chip address" */
306 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
307 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
308 /* 32 byte page write mode using*/
309 /* last 5 bits of the address */
311 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
312 #define CFG_EEPROM_PAGE_WRITE_ENABLE
314 /*-----------------------------------------------------------------------
315 * Cache Configuration
317 #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
318 /* have only 8kB, 16kB is save here */
319 #define CFG_CACHELINE_SIZE 32 /* ... */
320 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
321 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
324 /*-----------------------------------------------------------------------
325 * External Bus Controller (EBC) Setup
328 #define CAN_BA 0xF0000000 /* CAN Base Address */
329 #define DUART0_BA 0xF0000400 /* DUART Base Address */
330 #define DUART1_BA 0xF0000408 /* DUART Base Address */
331 #define RTC_BA 0xF0000500 /* RTC Base Address */
332 #define VGA_BA 0xF1000000 /* Epson VGA Base Address */
333 #define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
335 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
336 #define CFG_EBC_PB0AP 0x92015480
337 /*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
338 #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
340 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
341 #define CFG_EBC_PB1AP 0x92015480
342 #define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
344 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
345 #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
346 #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
348 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
349 #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
350 #define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
352 /* Memory Bank 4 (Epson VGA) initialization */
353 #define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
354 #define CFG_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
356 /*-----------------------------------------------------------------------
360 #define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
361 #define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
362 #define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
363 #define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
365 #define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
367 /*-----------------------------------------------------------------------
371 #define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
373 /* FPGA internal regs */
374 #define CFG_FPGA_CTRL 0x000
376 /* FPGA Control Reg */
377 #define CFG_FPGA_CTRL_CF_RESET 0x0001
378 #define CFG_FPGA_CTRL_WDI 0x0002
379 #define CFG_FPGA_CTRL_PS2_RESET 0x0020
381 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
382 #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
384 /* FPGA program pin configuration */
385 #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
386 #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
387 #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
388 #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
389 #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
391 /*-----------------------------------------------------------------------
392 * Definitions for initial stack pointer and data area (in data cache)
394 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
395 #define CFG_TEMP_STACK_OCM 1
397 /* On Chip Memory location */
398 #define CFG_OCM_DATA_ADDR 0xF8000000
399 #define CFG_OCM_DATA_SIZE 0x1000
400 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
401 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
403 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
404 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
405 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
407 /*-----------------------------------------------------------------------
408 * Definitions for GPIO setup (PPC405EP specific)
410 * GPIO0[0] - External Bus Controller BLAST output
411 * GPIO0[1-9] - Instruction trace outputs -> GPIO
412 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
413 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
414 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
415 * GPIO0[24-27] - UART0 control signal inputs/outputs
416 * GPIO0[28-29] - UART1 data signal input/output
417 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
419 #define CFG_GPIO0_OSRH 0x40000550
420 #define CFG_GPIO0_OSRL 0x00000110
421 #define CFG_GPIO0_ISR1H 0x00000000
422 #define CFG_GPIO0_ISR1L 0x15555440
423 #define CFG_GPIO0_TSRH 0x00000000
424 #define CFG_GPIO0_TSRL 0x00000000
425 #define CFG_GPIO0_TCR 0xF7FE0017
427 #define CFG_DUART_RST (0x80000000 >> 14)
428 #define CFG_LCD_ENDIAN (0x80000000 >> 7)
429 #define CFG_LCD0_RST (0x80000000 >> 30)
430 #define CFG_LCD1_RST (0x80000000 >> 31)
433 * Internal Definitions
437 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
438 #define BOOTFLAG_WARM 0x02 /* Software reboot */
441 * Default speed selection (cpu_plb_opb_ebc) in mhz.
442 * This value will be set if iic boot eprom is disabled.
445 #define PLLMR0_DEFAULT PLLMR0_266_133_66_33
446 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
449 #define PLLMR0_DEFAULT PLLMR0_200_100_50_33
450 #define PLLMR1_DEFAULT PLLMR1_200_100_50_33
453 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
454 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
457 #endif /* __CONFIG_H */