2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on include/configs/p1_p2_rdb_pc.h
5 * original copyright follows:
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
12 * QorIQ uCP1020-xx boards configuration file
17 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
18 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
19 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
20 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
21 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
22 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
24 #if defined(CONFIG_TARTGET_UCP1020T1)
26 #define CONFIG_UCP1020_REV_1_3
28 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
30 #define CONFIG_TSEC_ENET
33 #define CONFIG_HAS_ETH0
34 #define CONFIG_HAS_ETH1
35 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
36 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
37 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
38 #define CONFIG_IPADDR 10.80.41.229
39 #define CONFIG_SERVERIP 10.80.41.227
40 #define CONFIG_NETMASK 255.255.252.0
41 #define CONFIG_ETHPRIME "eTSEC3"
43 #ifndef CONFIG_SPI_FLASH
45 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
47 #define CONFIG_SYS_L2_SIZE (256 << 10)
49 #define CONFIG_LAST_STAGE_INIT
53 #if defined(CONFIG_TARGET_UCP1020)
55 #define CONFIG_UCP1020
56 #define CONFIG_UCP1020_REV_1_3
58 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
60 #define CONFIG_TSEC_ENET
64 #define CONFIG_HAS_ETH0
65 #define CONFIG_HAS_ETH1
66 #define CONFIG_HAS_ETH2
67 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
68 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
69 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
70 #define CONFIG_IPADDR 192.168.1.81
71 #define CONFIG_IPADDR1 192.168.1.82
72 #define CONFIG_IPADDR2 192.168.1.83
73 #define CONFIG_SERVERIP 192.168.1.80
74 #define CONFIG_GATEWAYIP 102.168.1.1
75 #define CONFIG_NETMASK 255.255.255.0
76 #define CONFIG_ETHPRIME "eTSEC1"
78 #ifndef CONFIG_SPI_FLASH
80 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
82 #define CONFIG_SYS_L2_SIZE (256 << 10)
84 #define CONFIG_LAST_STAGE_INIT
89 #define CONFIG_RAMBOOT_SDCARD
90 #define CONFIG_SYS_RAMBOOT
91 #define CONFIG_SYS_EXTRA_ENV_RELOC
92 #define CONFIG_SYS_TEXT_BASE 0x11000000
93 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
96 #ifdef CONFIG_SPIFLASH
97 #define CONFIG_RAMBOOT_SPIFLASH
98 #define CONFIG_SYS_RAMBOOT
99 #define CONFIG_SYS_EXTRA_ENV_RELOC
100 #define CONFIG_SYS_TEXT_BASE 0x11000000
101 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
104 #ifndef CONFIG_SYS_TEXT_BASE
105 #define CONFIG_SYS_TEXT_BASE 0xeff80000
107 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
109 #ifndef CONFIG_RESET_VECTOR_ADDRESS
110 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
113 #ifndef CONFIG_SYS_MONITOR_BASE
114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
119 #define CONFIG_ENV_OVERWRITE
121 #define CONFIG_SATA_SIL
122 #define CONFIG_SYS_SATA_MAX_DEVICE 2
123 #define CONFIG_LIBATA
126 #define CONFIG_SYS_CLK_FREQ 66666666
127 #define CONFIG_DDR_CLK_FREQ 66666666
129 #define CONFIG_HWCONFIG
132 * These can be toggled for performance analysis, otherwise use default.
134 #define CONFIG_L2_CACHE
137 #define CONFIG_ENABLE_36BIT_PHYS
139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
140 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
141 #define CONFIG_PANIC_HANG /* do not reset board on panic */
143 #define CONFIG_SYS_CCSRBAR 0xffe00000
144 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
146 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
148 #ifdef CONFIG_SPL_BUILD
149 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
153 #define CONFIG_DDR_ECC_ENABLE
154 #ifndef CONFIG_DDR_ECC_ENABLE
155 #define CONFIG_SYS_DDR_RAW_TIMING
156 #define CONFIG_DDR_SPD
158 #define CONFIG_SYS_SPD_BUS_NUM 1
159 #undef CONFIG_FSL_DDR_INTERACTIVE
161 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
162 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
163 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
164 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
167 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
169 /* Default settings for DDR3 */
170 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
171 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
172 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
173 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
174 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
175 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
177 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
178 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
179 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
180 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
182 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
183 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
184 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
185 #define CONFIG_SYS_DDR_RCW_1 0x00000000
186 #define CONFIG_SYS_DDR_RCW_2 0x00000000
187 #ifdef CONFIG_DDR_ECC_ENABLE
188 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
190 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
192 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
193 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
194 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
196 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
197 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
198 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
199 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
200 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
201 #define CONFIG_SYS_DDR_MODE_1 0x40461520
202 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
203 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
205 #undef CONFIG_CLOCKS_IN_MHZ
210 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
211 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
212 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
213 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
215 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
216 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
217 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
221 * Local Bus Definitions
223 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
224 #define CONFIG_SYS_FLASH_BASE 0xec000000
226 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
228 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
231 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
233 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
234 #define CONFIG_SYS_FLASH_QUIET_TEST
235 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
237 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
239 #undef CONFIG_SYS_FLASH_CHECKSUM
240 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
241 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
243 #define CONFIG_FLASH_CFI_DRIVER
244 #define CONFIG_SYS_FLASH_CFI
245 #define CONFIG_SYS_FLASH_EMPTY_INFO
246 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
248 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
250 #define CONFIG_SYS_INIT_RAM_LOCK
251 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
252 /* Initial L1 address */
253 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
254 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
255 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
256 /* Size of used area in RAM */
257 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
259 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
260 GENERATED_GBL_DATA_SIZE)
261 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
263 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
264 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
266 #define CONFIG_SYS_PMC_BASE 0xff980000
267 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
268 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
270 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
271 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
274 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
275 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
276 #ifdef CONFIG_NAND_FSL_ELBC
277 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
278 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
281 /* Serial Port - controlled on board with jumper J8
285 #define CONFIG_CONS_INDEX 1
286 #undef CONFIG_SERIAL_SOFTWARE_FIFO
287 #define CONFIG_SYS_NS16550_SERIAL
288 #define CONFIG_SYS_NS16550_REG_SIZE 1
289 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
290 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
291 #define CONFIG_NS16550_MIN_FUNCTIONS
294 #define CONFIG_SYS_BAUDRATE_TABLE \
295 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
297 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
298 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
301 #define CONFIG_SYS_I2C
302 #define CONFIG_SYS_I2C_FSL
303 #define CONFIG_SYS_FSL_I2C_SPEED 400000
304 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
305 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
306 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
307 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
308 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
309 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
310 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
312 #define CONFIG_RTC_DS1337
313 #define CONFIG_RTC_DS1337_NOOSC
314 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
315 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
316 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
317 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
320 * eSPI - Enhanced SPI
322 #define CONFIG_HARD_SPI
324 #define CONFIG_SF_DEFAULT_SPEED 10000000
325 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
327 #if defined(CONFIG_PCI)
330 * Memory space is mapped 1-1, but I/O space must start from 0.
333 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
334 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
335 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
336 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
337 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
338 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
339 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
340 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
341 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
342 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
344 /* controller 1, Slot 2, tgtid 1, Base address a000 */
345 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
346 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
347 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
348 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
349 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
350 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
351 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
352 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
353 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
355 #define CONFIG_CMD_PCI
357 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
358 #endif /* CONFIG_PCI */
363 #ifdef CONFIG_ENV_FIT_UCBOOT
365 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
366 #define CONFIG_ENV_SIZE 0x20000
367 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
371 #define CONFIG_ENV_SPI_BUS 0
372 #define CONFIG_ENV_SPI_CS 0
373 #define CONFIG_ENV_SPI_MAX_HZ 10000000
374 #define CONFIG_ENV_SPI_MODE 0
376 #ifdef CONFIG_RAMBOOT_SPIFLASH
378 #define CONFIG_ENV_IS_IN_SPI_FLASH
379 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
380 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
381 #define CONFIG_ENV_SECT_SIZE 0x1000
383 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
384 /* Address and size of Redundant Environment Sector */
385 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
386 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
389 #elif defined(CONFIG_RAMBOOT_SDCARD)
390 #define CONFIG_FSL_FIXED_MMC_LOCATION
391 #define CONFIG_ENV_SIZE 0x2000
392 #define CONFIG_SYS_MMC_ENV_DEV 0
394 #elif defined(CONFIG_SYS_RAMBOOT)
395 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
396 #define CONFIG_ENV_SIZE 0x2000
399 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
400 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
401 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
402 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
403 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
404 /* Address and size of Redundant Environment Sector */
405 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
406 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
411 #endif /* CONFIG_ENV_FIT_UCBOOT */
413 #define CONFIG_LOADS_ECHO /* echo on for serial download */
414 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
417 * Command line configuration.
419 #define CONFIG_CMD_REGINFO
424 #define CONFIG_HAS_FSL_DR_USB
426 #if defined(CONFIG_HAS_FSL_DR_USB)
427 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
429 #ifdef CONFIG_USB_EHCI_HCD
430 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
431 #define CONFIG_USB_EHCI_FSL
435 #undef CONFIG_WATCHDOG /* watchdog disabled */
438 #define CONFIG_FSL_ESDHC
439 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
440 #define CONFIG_MMC_SPI
441 #define CONFIG_CMD_MMC_SPI
444 /* Misc Extra Settings */
445 #undef CONFIG_WATCHDOG /* watchdog disabled */
448 * Miscellaneous configurable options
450 #define CONFIG_SYS_LONGHELP /* undef to save memory */
451 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
452 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
453 #if defined(CONFIG_CMD_KGDB)
454 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
456 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
458 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
459 /* Print Buffer Size */
460 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
461 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
462 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
465 * For booting Linux, the board info and command line data
466 * have to be in the first 64 MB of memory, since this is
467 * the maximum mapped by the Linux kernel during initialization.
469 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
470 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
472 #if defined(CONFIG_CMD_KGDB)
473 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
474 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
478 * Environment Configuration
481 #if defined(CONFIG_TSEC_ENET)
483 #if defined(CONFIG_UCP1020_REV_1_2)
484 #define CONFIG_PHY_MICREL_KSZ9021
485 #elif defined(CONFIG_UCP1020_REV_1_3)
486 #define CONFIG_PHY_MICREL_KSZ9031
488 #error "UCP1020 module revision is not defined !!!"
491 #define CONFIG_BOOTP_SERVERIP
493 #define CONFIG_MII /* MII PHY management */
494 #define CONFIG_TSEC1_NAME "eTSEC1"
495 #define CONFIG_TSEC2_NAME "eTSEC2"
496 #define CONFIG_TSEC3_NAME "eTSEC3"
498 #define TSEC1_PHY_ADDR 4
499 #define TSEC2_PHY_ADDR 0
500 #define TSEC2_PHY_ADDR_SGMII 0x00
501 #define TSEC3_PHY_ADDR 6
503 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
504 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
505 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
507 #define TSEC1_PHYIDX 0
508 #define TSEC2_PHYIDX 0
509 #define TSEC3_PHYIDX 0
511 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
515 #define CONFIG_HOSTNAME UCP1020
516 #define CONFIG_ROOTPATH "/opt/nfsroot"
517 #define CONFIG_BOOTFILE "uImage"
518 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
520 /* default location for tftp and bootm */
521 #define CONFIG_LOADADDR 1000000
523 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
525 #if defined(CONFIG_DONGLE)
527 #define CONFIG_EXTRA_ENV_SETTINGS \
528 "bootcmd=run prog_spi_mbrbootcramfs\0" \
529 "bootfile=uImage\0" \
530 "consoledev=ttyS0\0" \
531 "cramfsfile=image.cramfs\0" \
532 "dtbaddr=0x00c00000\0" \
533 "dtbfile=image.dtb\0" \
534 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
535 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
536 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
537 "fileaddr=0x01000000\0" \
538 "filesize=0x00080000\0" \
539 "flashmbr=sf probe 0; " \
540 "tftp $loadaddr $mbr; " \
541 "sf erase $mbr_offset +$filesize; " \
542 "sf write $loadaddr $mbr_offset $filesize\0" \
543 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
544 "protect off $nor_recoveryaddr +$filesize; " \
545 "erase $nor_recoveryaddr +$filesize; " \
546 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
547 "protect on $nor_recoveryaddr +$filesize\0 " \
548 "flashuboot=tftp $ubootaddr $ubootfile; " \
549 "protect off $nor_ubootaddr +$filesize; " \
550 "erase $nor_ubootaddr +$filesize; " \
551 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
552 "protect on $nor_ubootaddr +$filesize\0 " \
553 "flashworking=tftp $workingaddr $cramfsfile; " \
554 "protect off $nor_workingaddr +$filesize; " \
555 "erase $nor_workingaddr +$filesize; " \
556 "cp.b $workingaddr $nor_workingaddr $filesize; " \
557 "protect on $nor_workingaddr +$filesize\0 " \
558 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
559 "kerneladdr=0x01100000\0" \
560 "kernelfile=uImage\0" \
561 "loadaddr=0x01000000\0" \
562 "mbr=uCP1020d.mbr\0" \
563 "mbr_offset=0x00000000\0" \
564 "mmbr=uCP1020Quiet.mbr\0" \
566 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
568 "mmc write $loadaddr 1 1\0" \
569 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
570 "mmc erase 0x40 0x400; " \
571 "mmc write $loadaddr 0x40 0x400\0" \
573 "nor_recoveryaddr=0xEC0A0000\0" \
574 "nor_ubootaddr=0xEFF80000\0" \
575 "nor_workingaddr=0xECFA0000\0" \
576 "norbootrecovery=setenv bootargs $recoverybootargs" \
577 " console=$consoledev,$baudrate $othbootargs; " \
578 "run norloadrecovery; " \
579 "bootm $kerneladdr - $dtbaddr\0" \
580 "norbootworking=setenv bootargs $workingbootargs" \
581 " console=$consoledev,$baudrate $othbootargs; " \
582 "run norloadworking; " \
583 "bootm $kerneladdr - $dtbaddr\0" \
584 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
585 "setenv cramfsaddr $nor_recoveryaddr; " \
586 "cramfsload $dtbaddr $dtbfile; " \
587 "cramfsload $kerneladdr $kernelfile\0" \
588 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
589 "setenv cramfsaddr $nor_workingaddr; " \
590 "cramfsload $dtbaddr $dtbfile; " \
591 "cramfsload $kerneladdr $kernelfile\0" \
592 "prog_spi_mbr=run spi__mbr\0" \
593 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
594 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
595 "run spi__cramfs\0" \
596 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
597 " console=$consoledev,$baudrate $othbootargs; " \
598 "tftp $rootfsaddr $rootfsfile; " \
599 "tftp $loadaddr $kernelfile; " \
600 "tftp $dtbaddr $dtbfile; " \
601 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
602 "ramdisk_size=120000\0" \
603 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
604 "recoveryaddr=0x02F00000\0" \
605 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
606 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
607 "mw.l 0xffe0f008 0x00400000\0" \
608 "rootfsaddr=0x02F00000\0" \
609 "rootfsfile=rootfs.ext2.gz.uboot\0" \
610 "rootpath=/opt/nfsroot\0" \
611 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
612 "protect off 0xeC000000 +$filesize; " \
613 "erase 0xEC000000 +$filesize; " \
614 "cp.b $loadaddr 0xEC000000 $filesize; " \
615 "cmp.b $loadaddr 0xEC000000 $filesize; " \
616 "protect on 0xeC000000 +$filesize\0" \
617 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
618 "protect off 0xeFF80000 +$filesize; " \
619 "erase 0xEFF80000 +$filesize; " \
620 "cp.b $loadaddr 0xEFF80000 $filesize; " \
621 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
622 "protect on 0xeFF80000 +$filesize\0" \
623 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
624 "sf probe 0; sf erase 0x8000 +$filesize; " \
625 "sf write $loadaddr 0x8000 $filesize\0" \
626 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
627 "protect off 0xec0a0000 +$filesize; " \
628 "erase 0xeC0A0000 +$filesize; " \
629 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
630 "protect on 0xec0a0000 +$filesize\0" \
631 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
632 "sf probe 1; sf erase 0 +$filesize; " \
633 "sf write $loadaddr 0 $filesize\0" \
634 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
635 "sf probe 0; sf erase 0 +$filesize; " \
636 "sf write $loadaddr 0 $filesize\0" \
637 "tftpflash=tftpboot $loadaddr $uboot; " \
638 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
639 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
640 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
641 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
642 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
643 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
644 "ubootaddr=0x01000000\0" \
645 "ubootfile=u-boot.bin\0" \
646 "ubootd=u-boot4dongle.bin\0" \
647 "upgrade=run flashworking\0" \
648 "usb_phy_type=ulpi\0 " \
649 "workingaddr=0x02F00000\0" \
650 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
654 #if defined(CONFIG_UCP1020T1)
656 #define CONFIG_EXTRA_ENV_SETTINGS \
657 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
658 "bootfile=uImage\0" \
659 "consoledev=ttyS0\0" \
660 "cramfsfile=image.cramfs\0" \
661 "dtbaddr=0x00c00000\0" \
662 "dtbfile=image.dtb\0" \
663 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
664 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
665 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
666 "fileaddr=0x01000000\0" \
667 "filesize=0x00080000\0" \
668 "flashmbr=sf probe 0; " \
669 "tftp $loadaddr $mbr; " \
670 "sf erase $mbr_offset +$filesize; " \
671 "sf write $loadaddr $mbr_offset $filesize\0" \
672 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
673 "protect off $nor_recoveryaddr +$filesize; " \
674 "erase $nor_recoveryaddr +$filesize; " \
675 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
676 "protect on $nor_recoveryaddr +$filesize\0 " \
677 "flashuboot=tftp $ubootaddr $ubootfile; " \
678 "protect off $nor_ubootaddr +$filesize; " \
679 "erase $nor_ubootaddr +$filesize; " \
680 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
681 "protect on $nor_ubootaddr +$filesize\0 " \
682 "flashworking=tftp $workingaddr $cramfsfile; " \
683 "protect off $nor_workingaddr +$filesize; " \
684 "erase $nor_workingaddr +$filesize; " \
685 "cp.b $workingaddr $nor_workingaddr $filesize; " \
686 "protect on $nor_workingaddr +$filesize\0 " \
687 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
688 "kerneladdr=0x01100000\0" \
689 "kernelfile=uImage\0" \
690 "loadaddr=0x01000000\0" \
691 "mbr=uCP1020.mbr\0" \
692 "mbr_offset=0x00000000\0" \
694 "nor_recoveryaddr=0xEC0A0000\0" \
695 "nor_ubootaddr=0xEFF80000\0" \
696 "nor_workingaddr=0xECFA0000\0" \
697 "norbootrecovery=setenv bootargs $recoverybootargs" \
698 " console=$consoledev,$baudrate $othbootargs; " \
699 "run norloadrecovery; " \
700 "bootm $kerneladdr - $dtbaddr\0" \
701 "norbootworking=setenv bootargs $workingbootargs" \
702 " console=$consoledev,$baudrate $othbootargs; " \
703 "run norloadworking; " \
704 "bootm $kerneladdr - $dtbaddr\0" \
705 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
706 "setenv cramfsaddr $nor_recoveryaddr; " \
707 "cramfsload $dtbaddr $dtbfile; " \
708 "cramfsload $kerneladdr $kernelfile\0" \
709 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
710 "setenv cramfsaddr $nor_workingaddr; " \
711 "cramfsload $dtbaddr $dtbfile; " \
712 "cramfsload $kerneladdr $kernelfile\0" \
713 "othbootargs=quiet\0" \
714 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
715 " console=$consoledev,$baudrate $othbootargs; " \
716 "tftp $rootfsaddr $rootfsfile; " \
717 "tftp $loadaddr $kernelfile; " \
718 "tftp $dtbaddr $dtbfile; " \
719 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
720 "ramdisk_size=120000\0" \
721 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
722 "recoveryaddr=0x02F00000\0" \
723 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
724 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
725 "mw.l 0xffe0f008 0x00400000\0" \
726 "rootfsaddr=0x02F00000\0" \
727 "rootfsfile=rootfs.ext2.gz.uboot\0" \
728 "rootpath=/opt/nfsroot\0" \
730 "tftpflash=tftpboot $loadaddr $uboot; " \
731 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
732 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
733 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
734 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
735 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
736 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
737 "ubootaddr=0x01000000\0" \
738 "ubootfile=u-boot.bin\0" \
739 "upgrade=run flashworking\0" \
740 "workingaddr=0x02F00000\0" \
741 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
743 #else /* For Arcturus Modules */
745 #define CONFIG_EXTRA_ENV_SETTINGS \
746 "bootcmd=run norkernel\0" \
747 "bootfile=uImage\0" \
748 "consoledev=ttyS0\0" \
749 "dtbaddr=0x00c00000\0" \
750 "dtbfile=image.dtb\0" \
751 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
752 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
753 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
754 "fileaddr=0x01000000\0" \
755 "filesize=0x00080000\0" \
756 "flashmbr=sf probe 0; " \
757 "tftp $loadaddr $mbr; " \
758 "sf erase $mbr_offset +$filesize; " \
759 "sf write $loadaddr $mbr_offset $filesize\0" \
760 "flashuboot=tftp $loadaddr $ubootfile; " \
761 "protect off $nor_ubootaddr0 +$filesize; " \
762 "erase $nor_ubootaddr0 +$filesize; " \
763 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
764 "protect on $nor_ubootaddr0 +$filesize; " \
765 "protect off $nor_ubootaddr1 +$filesize; " \
766 "erase $nor_ubootaddr1 +$filesize; " \
767 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
768 "protect on $nor_ubootaddr1 +$filesize\0 " \
769 "format0=protect off $part0base +$part0size; " \
770 "erase $part0base +$part0size\0" \
771 "format1=protect off $part1base +$part1size; " \
772 "erase $part1base +$part1size\0" \
773 "format2=protect off $part2base +$part2size; " \
774 "erase $part2base +$part2size\0" \
775 "format3=protect off $part3base +$part3size; " \
776 "erase $part3base +$part3size\0" \
777 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
778 "kerneladdr=0x01100000\0" \
779 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
780 "kernelfile=uImage\0" \
781 "loadaddr=0x01000000\0" \
782 "mbr=uCP1020.mbr\0" \
783 "mbr_offset=0x00000000\0" \
785 "nor_ubootaddr0=0xEC000000\0" \
786 "nor_ubootaddr1=0xEFF80000\0" \
787 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
788 "run norkernelload; " \
789 "bootm $kerneladdr - $dtbaddr\0" \
790 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
791 "setenv cramfsaddr $part0base; " \
792 "cramfsload $dtbaddr $dtbfile; " \
793 "cramfsload $kerneladdr $kernelfile\0" \
794 "part0base=0xEC100000\0" \
795 "part0size=0x00700000\0" \
796 "part1base=0xEC800000\0" \
797 "part1size=0x02000000\0" \
798 "part2base=0xEE800000\0" \
799 "part2size=0x00800000\0" \
800 "part3base=0xEF000000\0" \
801 "part3size=0x00F80000\0" \
802 "partENVbase=0xEC080000\0" \
803 "partENVsize=0x00080000\0" \
804 "program0=tftp part0-000000.bin; " \
805 "protect off $part0base +$filesize; " \
806 "erase $part0base +$filesize; " \
807 "cp.b $loadaddr $part0base $filesize; " \
808 "echo Verifying...; " \
809 "cmp.b $loadaddr $part0base $filesize\0" \
810 "program1=tftp part1-000000.bin; " \
811 "protect off $part1base +$filesize; " \
812 "erase $part1base +$filesize; " \
813 "cp.b $loadaddr $part1base $filesize; " \
814 "echo Verifying...; " \
815 "cmp.b $loadaddr $part1base $filesize\0" \
816 "program2=tftp part2-000000.bin; " \
817 "protect off $part2base +$filesize; " \
818 "erase $part2base +$filesize; " \
819 "cp.b $loadaddr $part2base $filesize; " \
820 "echo Verifying...; " \
821 "cmp.b $loadaddr $part2base $filesize\0" \
822 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
823 " console=$consoledev,$baudrate $othbootargs; " \
824 "tftp $rootfsaddr $rootfsfile; " \
825 "tftp $loadaddr $kernelfile; " \
826 "tftp $dtbaddr $dtbfile; " \
827 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
828 "ramdisk_size=120000\0" \
829 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
830 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
831 "mw.l 0xffe0f008 0x00400000\0" \
832 "rootfsaddr=0x02F00000\0" \
833 "rootfsfile=rootfs.ext2.gz.uboot\0" \
834 "rootpath=/opt/nfsroot\0" \
835 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
836 "sf probe 0; sf erase 0 +$filesize; " \
837 "sf write $loadaddr 0 $filesize\0" \
838 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
839 "protect off 0xeC000000 +$filesize; " \
840 "erase 0xEC000000 +$filesize; " \
841 "cp.b $loadaddr 0xEC000000 $filesize; " \
842 "cmp.b $loadaddr 0xEC000000 $filesize; " \
843 "protect on 0xeC000000 +$filesize\0" \
844 "tftpflash=tftpboot $loadaddr $uboot; " \
845 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
846 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
847 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
848 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
849 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
850 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
851 "ubootfile=u-boot.bin\0" \
852 "upgrade=run flashuboot\0" \
853 "usb_phy_type=ulpi\0 " \
855 "setenv bootargs root=/dev/nfs rw " \
856 "nfsroot=$serverip:$rootpath " \
857 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
858 "console=$consoledev,$baudrate $othbootargs;" \
859 "tftp $loadaddr $bootfile;" \
860 "tftp $fdtaddr $fdtfile;" \
861 "bootm $loadaddr - $fdtaddr\0" \
863 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
864 "console=$consoledev,$baudrate $othbootargs;" \
866 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
867 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
868 "bootm $loadaddr - $fdtaddr\0" \
870 "setenv bootargs root=/dev/ram rw " \
871 "console=$consoledev,$baudrate $othbootargs " \
872 "ramdisk_size=$ramdisk_size;" \
874 "fatload usb 0:2 $loadaddr $bootfile;" \
875 "fatload usb 0:2 $fdtaddr $fdtfile;" \
876 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
877 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
879 "setenv bootargs root=/dev/ram rw " \
880 "console=$consoledev,$baudrate $othbootargs " \
881 "ramdisk_size=$ramdisk_size;" \
883 "ext2load usb 0:4 $loadaddr $bootfile;" \
884 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
885 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
886 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
888 "setenv bootargs root=/dev/$jffs2nor rw " \
889 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
890 "bootm $norbootaddr - $norfdtaddr\0 " \
892 "setenv bootargs root=/dev/ram rw " \
893 "console=$consoledev,$baudrate $othbootargs " \
894 "ramdisk_size=$ramdisk_size;" \
895 "tftp $ramdiskaddr $ramdiskfile;" \
896 "tftp $loadaddr $bootfile;" \
897 "tftp $fdtaddr $fdtfile;" \
898 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
903 #endif /* __CONFIG_H */